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Published online by Cambridge University Press: 01 February 2011
High quality strained Ge (s-Ge) epitaxial layers are a promising candidate to achieve high mobility channel MOSFETs suitable for the 22 nm technology node and beyond, due to the intrinsically higher mobility of Ge compared to Si, and the additional performance enhancements from strain [1]. In order to achieve an s-Ge channel more than a few monolayers thick it is necessary to engineer a relaxed Si1-xGex buffer with a high Ge content (x > 0.5). We have recently reported high quality s-Ge layers grown by RP-CVD at low temperature (T ≤ 450 °C), on a fully relaxed Si0.2Ge0.8 buffer [2]. By using a reverse-grading approach, we achieved a high Ge composition in the buffer, with a smooth surface (rms surface roughness of ~2 nm), low threading dislocations density (~ 4 x 106 cm-2) and much thinner (~ 2.1 μm) than can be achieved with conventional linear grading [3].
In this work, the thermal stability of s-Ge epilayers (up to 80 nm thick) grown on relaxed Si0.2Ge0.8 buffers has been investigated by in-situ annealing in H2 ambient at temperatures up to 650 °C. These temperatures are similar to those currently used during fabrication of advanced CMOS devices. All s-Ge layers were grown at 400 °C using GeH4 gaseous precursor. The relaxation of the annealed layers has been studied using high-resolution XRD reciprocal space maps (RSMs), and was found to depend strongly on both annealing temperature and thickness of the Ge epilayer. Strained Ge layers up to 50 nm thick remained fully strained after annealing at 450 °C, whereas after annealing at 550 °C s-Ge layers thicker than 20 nm were on the onset of relaxation; after annealing at 650 °C all s-Ge layers showed significant relaxation with defects clearly visible at the Si0.2Ge0.8/Ge interface. All annealed s-Ge layers exhibited higher surface roughness than s-Ge control samples without annealing (rms ~ 2 nm). Annealing at 450 °C resulted in only a slight increase in surface roughness (rms ~ 3 nm), almost independent of s-Ge thickness. However, annealing at 550 °C and 650 °C resulted in significant surface roughening (with maximum rms values of 5 nm and 35 nm, respectively) due to the formation of Ge islands, which were observed by AFM. At these higher temperatures, the surface roughness of the s-Ge layers was found to be thickness dependent, with a Ge smoothing effect observed for layers greater than 50 nm.
These results are particularly important for the fabrication of s-Ge MOSFETs, for which the surface passivation prior to gate stack formation is critical to the performance of the device. Based on the results presented here, the thermal budget should be kept below 550 °C to avoid relaxation and roughening of the s-Ge epilayer, which could degrade the device performance.