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Issues and Optimization of Millisecond Anneal Process for 45 nm node and beyond

Published online by Cambridge University Press:  01 February 2011

Kanna Adachi ,
Kazuya Ohuchi ,
Nobutoshi Aoki ,
Hideji Tsujii ,
Takayuki Ito ,
Hiroshi Itokawa ,
Koji Matsuo ,
Honguh Yoshinori ,
Naoki Tamaoki  and
Kazunari Ishimaru
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Kanna Adachi
Affiliation:
kanna.adachi@toshiba.co.jp, Toshiba corporation Semiconductor Company, SoC Research & Development Center, 8,Shinsugita-Cho,Isogo-Ku, Yokohama, N/A, 235-8522, Japan, +81-45-770-3638, +81-45-770-3571
Kazuya Ohuchi
Affiliation:
kazuya.ohuchi@toshiba.co.jp, Toshiba Corporation, SoC Research & Development Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
Nobutoshi Aoki
Affiliation:
nobutoshi.aoki@toshiba.co.jp, Toshiba Corporation, SoC Research & Development Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama,, N/A, 235-8522, Japan
Hideji Tsujii
Affiliation:
hideji.tsujii@toshiba.co.jp, Toshiba Corporation, SoC Research & Development Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
Takayuki Ito
Affiliation:
t-ito@amc.toshiba.co.jp, Toshiba Corporation,, Process & Manufacturing Engineering Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
Hiroshi Itokawa
Affiliation:
hiroshi.itokawa@toshiba.co.jp, Toshiba Corporation, Process & Manufacturing Engineering Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
Koji Matsuo
Affiliation:
koji.matsuo@toshiba.co.jp, Toshiba Corporation, Process & Manufacturing Engineering Center, Semiconductor Company,, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, 235-8522, N/A, Japan
Honguh Yoshinori
Affiliation:
yoshinori.honguh@toshiba.co.jp, Toshiba Corporation, Corporate R & D Center, 1 Komukai Toshiba-cho, Saiwai-ku,, Kawasaki, N/A, 242-8582, Japan
Naoki Tamaoki
Affiliation:
tamaoki@msl.rdc.toshiba.co.jp, Toshiba Corporation, Corporate R & D Center, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, N/A, 242-8582, Japan
Kazunari Ishimaru
Affiliation:
kazu.ishimaru@toshiba.co.jp, Toshiba Corporation, SoC Research & Development Center, Semiconductor Company, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
Hidemi Ishiuchi
Affiliation:
hidemi.ishiuchi@toshiba.co.jp, Toshiba Corporation, SoC Research & Development Center, Semiconductor Company, 8,Shinsugita-Cho,Isogo-Ku,, Yokohama, N/A, 235-8522, Japan
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Abstract

We have investigated MSA, namely, Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA), dopant activation technology of source/drain extension for 45 nm node, which can be substituted for spike RTA. Since it is possible to achieve a similar relation between a sheet resistance and a junction depth by using either FLA or LSA, both annealing methods are capable of providing the junction characteristics required by the ITRS target. However, we have noticed that there are three crucial issues from the viewpoints of device integration and CMOSFET performance: junction leakage current, gate leakage current and pattern dependence. In this report, we discuss these issues and indicate how to cope with them.

Keywords

annealinglaser annealingdiffusion
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 912: Symposium C – Doping Engineering for Device Fabrication , 2006 , 0912-C04-06
Copyright
Copyright © Materials Research Society 2006

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References

1 http://public.itrs.net/Google Scholar
2 Shima, A., Wang, Y., Talwar, S., and Hirakawa, A., Symp. VLSI Tech. Dig., 174, (2004).Google Scholar
3 Shima, A., Wang, Y., Upadhyaya, D., Feng, L., Talwar, S., and Hirakawa, A., Symp. VLSI Tech. Dig., 144, (2005).Google Scholar
4 Ito, T., Suguro, K., Itani, T., Nishinohara, K., Matsuo, K. and Saito, T., Symp. VLSI Tech. Dig., 53, (2003).Google Scholar
5 Ootsuka, F., Ozaki, H., Sasaki, T., Yamashita, K., Takada, H., Izumi, N., Nakagawa, Y., Hayashi, M., Kiyono, K., Yasuhira, M., and Arikado, T., IEDM Tech. Dig., 647, (2003).Google Scholar
6 Ito, T., Iinuma, T., Murakoshi, A., Akutsu, H., Suguro, K., Arikado, T., Okumura, K., Yoshioka, M., Owada, T., Imaoka, Y., Murayama, H., and Owada, T., Jpn. J. Appl. Phys. 41, 2394, (2002).Google Scholar
7 Ito, T., Matsuo, K., Itokawa, H., Itani, T., Tamaoki, N., Honguh, Y., Suguro, K., Yokomori, T., Owada, T., Goto, Y., Nozaki, Y., Murayama, H., Kiyama, H., and Kusuda, T., IWJT Extended Abstract, 59, (2005).Google Scholar