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Low Temperature Bonding via Copper Nanowires for 3D Integrated Circuits

Published online by Cambridge University Press:  01 February 2011

Shu Rong Chun
Affiliation:
chun0048@ntu.edu.sg, Nanyang Technological University, Materials Science and Engineering, Singapore, Singapore
Wardhana Aji Sasangka
Affiliation:
wardh.was@gmail.com, Nanyang Technological University, Materials Science and Engineering, Singapore, Singapore
Chee Lip Gan
Affiliation:
clgan@ntu.edu.sg, Nanyang Technological University, Materials Science and Engineering, Singapore, Singapore
Hui Cai
Affiliation:
CaiHui@ntu.edu.sg, Nanyang Technological University, Materials Science and Engineering, Singapore, Singapore
Chee Mang Ng
Affiliation:
ngcm@globalfoundries.com, GLOBALFOUNDRIES Singapore Pte Ltd, Singapore, Singapore
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Abstract

Low temperature bonding is desired for compatibility with back-end-of-line processing (BEOL) conditions in order not to affect the three dimensional (3D) Integrated Circuits (IC) device performance. In this paper, the aim is to demonstrate that thermocompression bonding temperature can be lowered by changing the copper (Cu) film with Cu nanowires fabricated via electrodeposition through anodized aluminum oxide (AAO) template. A comparison was done between film-to-film (Film-Film) and nanowires-to-nanowires (NWs-NWs) bonding in terms of microstructure and shear strength. Cross-sectional images captured by Focused Ion Beam (FIB) revealed good interface between NWs-NWs bonding as the nanowires had fused together. Scanning Electron Microscope (SEM) images of samples after shear test also demonstrated that there is good adhesion between the bonding layers. Results from shear tests showed an increase in shear strength of NWs-NWs bonding as compared to that of Film-Film bonding at 200 °C. In addition, NWs-NWs bonding at 300 °C achieved higher shear strength than at 200 °C. In this study, it has been shown that copper nanowires fabricated via electrodeposition through porous AAO template can be a potential method to form a bonding intermediate layer for 3D ICs.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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