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Materials Challenges for CMOS Junctions

Published online by Cambridge University Press:  17 March 2011

William J. Taylor ,
Michael J. Rendon ,
Eric Verret ,
Jack Jiang ,
Cristiano Capasso ,
Dave Sing ,
Jen-Yee Nguyen ,
James Smith ,
Eric Luckowski  and
Arturo Martinez
...Show all authors
William J. Taylor
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Michael J. Rendon
Affiliation:
Motorola CMOS Platform Device Development Mail Drop K-10, 3501 Ed Bluestein Blvd., Austin, Texas, USA, 78721
Eric Verret
Affiliation:
Motorola CMOS Platform Device Development Mail Drop K-10, 3501 Ed Bluestein Blvd., Austin, Texas, USA, 78721
Jack Jiang
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Cristiano Capasso
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Dave Sing
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Jen-Yee Nguyen
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
James Smith
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Eric Luckowski
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Arturo Martinez
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Jamie Schaeffer
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
Phil Tobin
Affiliation:
Motorola Advanced Products R&D Lab, Austin, Texas, USA 78721
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Abstract

Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 810: Symposium C – Silicon Front-End Junction Formation-Physics and Technology , 2004 , C1.1
Copyright
Copyright © Materials Research Society 2004

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References

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