Hostname: page-component-6bf8c574d5-xtvcr Total loading time: 0 Render date: 2025-02-22T08:15:37.697Z Has data issue: false hasContentIssue false
  • English
  • Français

Materials, Mechanical, and Thermal Considerations of High Density Multi-Chip Electronic Packages

Published online by Cambridge University Press:  21 February 2011

J. Peter Krusius
J. Peter Krusius*
Affiliation:
Cornell University, School of Electrical Engineering, Ithaca, New York 14853-5401, USA
Get access

Abstract

Multi-chip packages (MCP) are analyzed for high density CMOS packaging using package system simulation, a new systematic methodology for design and trade-off studies of electronic packages. Technology parameters for a representative CMOS chip, multi-chip package, and printed wiring board technology are defined. The effect of these technology parameters on the characteristics of the MCP are examined. The MCP's are optimized using simulated annealing. A large set of optimum MCP's has been found. Based on this set, MCP technology parameters are ranked and their implications on future high density MCP's discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 167: Symposium K – Advanced Electronic Packaging Materials , 1989 , 23
Copyright
Copyright © Materials Research Society 1990

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. See e.g.Tummala, R.R and Rymaszewski, E.J. (eds)., Microlectronic Packaging Handbook. (Van Nostrand Reinhold, New York, 1989).Google Scholar
2. Blodgett, A.J., IBM J. Res. Develop. 26, 30 (1981).Google Scholar
3. Pence, W.E. and Krusius, J.P., System Packaging Tradeoff Modeling, invited paper, presented at the 1988 IEEE Computer Packaging Workshop, May 1988, Pocono, PA (unpublished).Google Scholar
4. Pence, W.E., PhD Thesis, Cornell University, New York, May 1989 (unpublished)Google Scholar
5. Pence, W.E. and Krusius, J.P., article in preparation for periodical journal.Google Scholar
6. Heller, W.R., Hsi, O.G., Mikhail, W.F., IEEE Design and Test, 43 (May 1984).Google Scholar
7. Hannemann, R., IEEE-OH, 48 ( May 1986).Google Scholar
8. Pence, W. E. and Krusius, J. P., Packaging Design and Analysis via System Analysis. Proceedings of 1989 Electronic Materials and Processing Congress (Microelectronic Packaging Technology, Materials and Processes, ASM International, 1989) pp. 103–108,Google Scholar
9. Krusius, J. P. and Pence, W. E., Multi-Chip Packaging Tradeoffs for CMOS and Bipolar IC's, Proceedings of National Electronic Packaging and Production Conference (NEPCON, Anaheim, CA, 1989) pp. 125–130.Google Scholar
10. Krusius, J. P. and Pence, W. E., Analysis of Materials and Structure Tradeoffs in Thin and Thick Film Multi-ChiD Packages, Proceedings of 1989 Electronic Components Conference (IEEE, NY, 1989) pp. 641–646.Google Scholar
11. Krusius, J. P. and Pence, W. E., Potential of Low Temperature CMOS with Superconductive Interconnect. Proceedings of the IEEE VLSI Multi-Level Interconnection Conference (IEEE, NY, 1989) pp. 233–240.Google Scholar
12. Huang, J.S.T. and Shrankler, J.W., IEEE Trans. on Electron Devices ED–34, 101 (1987)Google Scholar