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Measurements of Enhanced Diffusion of Buried Layers in Silicon Membrane Structures During Oxidation

Published online by Cambridge University Press:  25 February 2011

Scott T. Dunham ,
Anuradha M. Agarwal  and
Nanseng Jeng
Scott T. Dunham
Affiliation:
Boston University, Electrical, Computer and Systems Engineering Department, 44 Cummington Street, Boston, MA 02215.
Anuradha M. Agarwal
Affiliation:
Boston University, Electrical, Computer and Systems Engineering Department, 44 Cummington Street, Boston, MA 02215.
Nanseng Jeng
Affiliation:
Boston University, Electrical, Computer and Systems Engineering Department, 44 Cummington Street, Boston, MA 02215.
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Abstract

Reported calculations of the diffusion coefficient of silicon self interstitials vary over several orders of magnitude at temperatures of interest for integrated circuit fabrication. In this work, we measure the enhanced diffusion of phosphorus buried layers while interstitials are injected at a wafer surface via thermal oxidation. The starting substrates were either float-zone silicon or Czochralski silicon with a pre-treatment to precipitate excess oxygen. The samples were prepared by implantation of phosphorus followed by the growth of a 40-60µm epitaxial layer. They were then etched anisotropically from the frontside or backside to yield membrane structures. Local oxidation was performed at 1100°C on either the frontside or backside of each wafer and buried layer diffusion was monitored, yielding information about interstitial diffusion in silicon and it’s dependence on bulk properties.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 163: Symposium G – Impurities, Defects and Diffusion in Semiconductors: Bulk and Layered Structures , 1989 , 543
Copyright
Copyright © Materials Research Society 1990

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