Hostname: page-component-78c5997874-8bhkd Total loading time: 0 Render date: 2024-11-13T02:06:30.681Z Has data issue: false hasContentIssue false
  • English
  • Français

Nanoporous Silica For Low K Dielectrics

Published online by Cambridge University Press:  10 February 2011

T. Ramos ,
K. Rhoderick ,
R. Roth ,
L. Brungardt ,
S. Wallace ,
J. Drage ,
J. Dunne ,
D. Endisch ,
R. Katsanes  and
N. Viemes
...Show all authors
T. Ramos
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
K. Rhoderick
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
R. Roth
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
L. Brungardt
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
S. Wallace
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
J. Drage
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
J. Dunne
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
D. Endisch
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
R. Katsanes
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
N. Viemes
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
D. M. Smith
Affiliation:
Nanoglass LLC, 1349 Moffett Park Drive., Sunnyvale, CA 95089, USA
Get access

Abstract

As integrated circuit sizes decrease below 0.25 microns, device performance will no longer improve at the same rate as for past generations because of RC interconnect delay which becomes significant as compared to the intrinsic gate delay. Parallel approaches to address this are to use a lower resistance metal (i.e., copper instead of aluminum) and to use a dielectric material with a dielectric constant significantly below that of dense silica (∼4). Recently, considerable progress has been made in development of thin films of nanoporous silica for these applications. Advantages include high thermal stability, small pore size, similarity to conventional spin-on deposition processes and spin-on glass precursors and final material (silica). The dielectric constant of nanoporous silica can be tailored between ∼1 and 3 which allows its’ implementation at multiple technology nodes in integrated circuit manufacture.

Recent development efforts have been focused on; 1) simpler and more reproducible deposition processes, 2) a more complete understanding of processing-property relationships for this material, 3) scale-up of manufacturing to yield a range of precursor products with stability for at least six months and very high purity, and 4) working with customers to integrate this material into both aluminum/gapfill and copper/damascene process flows. This paper targets several specific issues related to nanoporous silica use including water adsorption, pore size distribution control, processing at commercially viable throughputs, and obtaining thickness and dielectric uniformity across 200 mm wafers and wafer to wafer.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 511: Symposium E – Low Dielectric Constant Materials IV , 1998 , 105
Copyright
Copyright © Materials Research Society 1998

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 The National Technology Roadmap for Semiconductors, SIA, San Jose, CA (1997)Google Scholar
2 Lee, W.W. and Ho, P.S., MRS Bulletin, 22, 19, (1997).Google Scholar
3 Hrubesh, L.W., Keene, L.E., and Latorre, V.R., J. Mater.Res., 8, 1736, (1993).Google Scholar
4 Smith, D.M, Anderson, J.M., Cho, C.C. and Gnade, B.E., Advances in Porous Materials, edited by Komareni, S., Smith, D.M. and Beck, J.S., Mater.Res.Soc. 371, 261, Pittsburgh, PA, 1995.Google Scholar
5 Smith, D.M., Anderson, J. M., Cho, C.C., Johnston, G.P., and Jeng, S.P., Low Dielectric Constant Materials, Mater.Res.Soc. 381, 261, Pittsburgh, PA, 1995.Google Scholar
6 Cho, C.C., Gnade, B., Smith, D.M., US patents #5,470,802, #5,494,858, #5,504,042, num;5,523,615 (1995)Google Scholar
7 Jin, C., Luttmer, J.D., Smith, D.M., and Ramos, T., MRS Bulletin, 22, 39, (1997).Google Scholar
8 Ramos, T., Roderick, K., Maskara, A., and Smith, D.M., Advanced Metallization and Interconnect Systems for ULSI Applications. 1996, Mater.Res.Soc., 455, Pittsburgh, PA, 1996.Google Scholar
9 Chow, L.A., Yu, T., Dunn, B.S., Tu, K.N., and. Chiang, , Low Dielectric Constant MaterialsllI, Mater.Res.Soc. 476, 105, Pittsburgh, PA, 1997.Google Scholar
10 Haereid, S., Anderson, J., Einarsrud, M.A., Hua, D.W., Smith, D.M., JNCS, 185, 221 (1995)Google Scholar
11 Hua, D.W., Anderson, J., DiGregorio, J., Smith, D.M. and Beaucage, G., JNCS, 186, 142 (1995)Google Scholar
12 Ramos, T. and co-workers, US Patent Application, 1998.Google Scholar
13 Smith, D.M., Johnston, G., Maskara, A., Ramos, T., Jeng, S.P., Gnade, B.E., and Jin, C.M., WTC Patent Appl, (1996)Google Scholar
14 Patents pendingGoogle Scholar