Article contents
Reliability Aspects of Thin Dielectric Films Used in NVM ICs
Published online by Cambridge University Press: 15 February 2011
Abstract
The behavior of small MOS structures with polycrystalline silicon gates subjected to stresses caused by electron injection was analyzed. A nature of degradation in MOS structures is more clearly and reliably extracted from the investigations of the microstructures with active areas less than 10 μm2. NVM cells with floating gate are convenient objects for such investigations. Due to the high current sensitivity and range of described novel techniques (10-17 - 10-7 A), small tunnel oxide area in memory cell (1-5 μm2) and temperature measurements (120 - 438 K) some new results in oxide degradation have been found.
In this work the following chain of degradation processes during electron injection was experimentally detected: conversion from planar to local injection (area of localization~10-3 um2) => appearance of percolated path for low field leakage (it is defined by sufficient amount of generated deep level traps in dielectric Nt~ 1020 cm-3) => development of leakage channel into the breakdown region. TDDB method usually developed on large MOS structures with electrostatic energy more than critical value 107 eV is not able to distinguish this chain and correctly evaluate degradation. Taking into account a localization of electron injection, it was found that the charge to the leakage channel generation is about 104 -105 Cl/cm2 for cells without fabrication defects. A kinetics of localization is very sensitive to the tunnel oxidation process.
Degradation stages of NVM cells, subjected to different electric stresses and anneals, have been investigated in wide current and temperature ranges. Polaron and Trap Model for the I-V leakage characteristics of degraded SiO2 films is presented.
- Type
- Research Article
- Information
- Copyright
- Copyright © Materials Research Society 1995
References
- 2
- Cited by