Hostname: page-component-cd9895bd7-p9bg8 Total loading time: 0 Render date: 2024-12-28T22:17:43.823Z Has data issue: false hasContentIssue false

Silicon Interposer Reliability Optimization through Process-Oriented Stress Modeling

Published online by Cambridge University Press:  30 July 2012

Sri Ramakanth Kappaganthu
Affiliation:
Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh 500032, India
Aditya Karmarkar
Affiliation:
Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh 500032, India
Xiaopeng Xu
Affiliation:
Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, U.S.A.
Get access

Abstract

A process-oriented stress modeling methodology is developed to investigate the stress evolution during the silicon interposer packaging process. An FEM based 3D TCAD simulator is used to perform the process steps to construct the silicon interposer stack in sequential order. These steps include TSV fabrication for passive silicon interposer, micro-bumping and reflow process for integrating active dies and passive interposer, C4-bumping and reflow for interposer BT-substrate stacking, and epoxy mold curing for interposer encapsulation. Stress simulations are carried out for each process step to obtain accurate stress evolution history. To resolve micron features within millimeter structures, the modeling strategy employs symmetry conditions, and equivalent materials for regions away from structure features of interest. The detailed structure includes 3x3 arrays of microbumps, TSV arrays, and C4-bumps with multiple material layers at the stack corner. Important design parameters include interposer thickness and edge clearance. For different silicon interposer configurations critical stresses in the outmost microbump and C4-bump are analyzed and compared. The reliability implications are discussed.

Type
Articles
Copyright
Copyright © Materials Research Society 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. He, D. et al. ., Elec. Comp. & Tec. Con., 2005, 349.Google Scholar
2. van Silfhout, R.B.R, et al. ., Elec. Comp. & Tec. Con., 2002, 1182.Google Scholar
3. Chong, D. Y. R. et al. ., Proceedings of IPACK03, 2003, 35335.Google Scholar
4. Park, S. et al. . , IEEE Trans. Comp & Pack. Tech., 2007, 294.Google Scholar
5. Jong, W.-R. et al. ., ANTEC, 2005, 1665.Google Scholar
6. Zhai, C.J. et al. ., Mat. Res. Soc. Symp. Proc., 2004, F1.8.1.Google Scholar
7. TCAD Sentaurus Interconnect User Guide, Synopsys, Inc., Sep. 2011.Google Scholar