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Via-Hole Addressed TFT and Process for Large-Area A-Si:H Electronics

Published online by Cambridge University Press:  15 February 2011

H. Gleskova
Affiliation:
Princeton University, Department of Electrical Engineering, Princeton, NJ 08544
S. Wagneri
Affiliation:
Princeton University, Department of Electrical Engineering, Princeton, NJ 08544
D. S. Shen
Affiliation:
University of Alabama in Huntsville, Department of Electrical and Computer Engineering, Huntsville, AL 35899
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Abstract

We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. All gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 μm in 50 μm glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

Type
Research Article
Copyright
Copyright © Materials Research Society 1997

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References

REFERENCES

1. Howard, W.E., Journal of the Society for Information Display 3, 127 (1995).Google Scholar
2. Kaneko, E., in Society for Information Display Digest of Technical Papers. Vol. XXVI (Society for Information Display, Santa Ana, CA, 1995), pp. 150153.Google Scholar
3. Gleskova, H., Wagner, S. and Shen, D.S., IEEE Electron Device Lett. 16, 418 (1995).Google Scholar
4. Gleskova, H., Könenkamp, R., Wagner, S. and Shen, D.S., IEEE Electron Device Lett. 17, 264 (1996).Google Scholar
5. Resonetics, Inc., 4 Bud Way, Suite 21, Nashua, NH 03063.Google Scholar