The paper presents the results of studies on the effect of transistor DC operating conditions on GaN power amplifiers’ (PAs) power efficiency and linearity improved by digital predistortion (DPD). The single-ended 10 W (ISM2.45 GHz) and 150 W (3.4/3.6 GHz) GaN HEMT PAs excited by wideband LTE20 E-TM1.1 signal were tested. To check the applicability of the small-signal approach for designing of LTE signals’ PAs, the 150 W PA using transistor model extracted from S-parameters measured at the properly selected operating points was designed. The conventional DPD based on the indirect learning architecture and the memory polynomial model of PA non-linearity was implemented. The results of the research show that in case of class A and B PAs operating up to several dozen watts, an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor can be achieved. However, a noticeable ACLR improvement with a coincident increase in power-added efficiency (PAE) can be obtained by choosing the compromise DC operating point and using DPD. In the case of high-PAs, the linearity and efficiency are strongly dependent on the load of a transistor, thus the role of DPD is significantly increased.

This paper presents a fully digital transmitter chain from baseband to antenna, including a modulator, two truly digital (i.e. fully switched) microwave power amplifiers and a transmit/receive switch. Both, amplifier and switch monolithic microwave integrated circuits were implemented in a GaN HEMT process. The novel amplifier design provides greatly reduced complexity, needing only three voltage sources. Measurements were conducted using 5, 20, and 100 MHz wide baseband signals. Carrier frequencies cover the 900 and 2000 MHz bands. For the 5 MHz BB signal an ACLR of over 52 dB is reached, fulfilling the 3GPP specs for base station use while still maintaining a final-stage drain efficiency of 46% at 6.5 dB peak to average power ratio. Full-scale output power at 30 V supply voltage was measured to exceed 3 W at 80% drain efficiency. Further features of this digital amplifier approach include small form factor and frequency agility, making it an ideal candidate for software defined radio.

This paper presents for the first time a wavetable-based coding scheme to generate a high-speed binary input signal for digital RF power amplifiers. The approach maximizes the utilization of the time domain handling capabilities of the pulse forming circuit. Key features are a greatly improved output spectrum purity in comparison with common digital modulators, the ability to adjust the modulator to any given pulse forming hardware and a built-in signal correction option that comes without additional computational cost. To give a first impression on the modulators behavior and its possibilities to adapt to different hardware constraints, simulations are carried out for different parameter variations and for different baseband bandwidths. Furthermore, the proposed concept is emulated with an arbitrary waveform generator to gather additional measurement data. For a 5 MHz wideband code division multiple access (WCDMA) signal (6.5 dB peak-to-average power ratio) at 900 MHz, an error vector magnitude (EVM) of 0.26% and better than >58 dB adjacent channel leakage ratio (ACLR) were recorded. To the authors’ knowledge, these are the best values achieved so far for a single-bit coding scheme without digital predistortion that still maintains maximum power coding efficiency.

This paper presents a full-duplex dual-band orthogonal frequency division duplexing (OFDM) radio architecture that enables the radio transceiver to be more flexible and provides a viable radio link capacity gain. A simple but practical I/Q imbalance estimation and compensation method, based on the frequency-flat-fading behavior of the self-interference channel, is proposed. The performance of the proposed I/Q imbalance compensation method is evaluated by link level simulation conducted with Advanced Design System and Matlab. The co-simulation results show that the proposed radio transceiver could potentially increase the physical layer transmission rate by four times compared with the conventional radio link at the cost of tolerable loss of bit error rate performance. The I/Q imbalance compensation method can effectively compensate both high and low I/Q imbalance without the problem of algorithm convergence.

Directional modulation (DM) is an emerging technology for securing wireless communications at the physical layer. This promising technology, unlike the conventional key-based cryptographic methods and the key-based physical layer security approaches, locks information signals without any requirements of keys. The locked information can only be fully recovered by the legitimate receiver(s) priory known by DM transmitters. This paper reviews the origin of the DM concept and, particularly, its development in recent years, including its mathematical model, assessment metrics, synthesis approaches, physical realizations, and finally its potential aspects for future studies.

This paper presents results of direction of arrival (DOA) estimation using multiple signal classification (MUSIC), Root-MUSIC, and estimation of signal parameters via rotational invariance technique algorithms. As is well known, these algorithms are mainly based on the specific properties of the signal covariance matrix as well as the decomposition of the observation space into two subspaces, one for the signal and the other for the noise. Here, we are particularly interested in the quality of sources localization considering only the case of uncorrelated radio frequency signals impinging on an antenna array. A measurement system consisting of a linear array antenna and a five-port network applicable to a demodulator such as a receiver is used for the DOA estimation process. Co-simulations performed with the Advanced Device System and Matlab yielded interesting results not only on their performance but also on their limitation.

Multipath propagation is still one of the major problems in local positioning systems today. Especially in indoor environments, the received signals are disturbed by blockages and reflections. This can lead to a large bias in the user's time-of-arrival (TOA) value. Thus multipath is the most dominant error source for positioning. In order to improve the positioning performance in multipath environments, recent multipath mitigation algorithms based upon the concept of sequential Bayesian estimation are used. The presented approach tries to overcome the multipath problem by estimating the channel dynamics, using unscented Kalman filters (UKF). Simulations on artificial and measured channels from indoor as well as outdoor environments show the profit of the proposed estimator model. Furthermore, the quality of channel estimation applying the UKF and the channel sounding capabilities of the estimator are shown.

The large bandwidth of the 60 GHz frequency band enables wireless short-range applications with data rates of several Gbit/s. The German project EASY-A has focused on early prototype implementations for selected applications, although no generally accepted 60 GHz standard has been available at the time. The implementations are based on application-oriented physical layer designs and link-budget investigations that account for the scenario-specific channel characteristics and for different integration technologies. This paper discusses the results of these investigations and details the hardware implementation of the digital baseband processing that relies on considerable parallelization. The link-budget results show that SiGe technology allows for 1 Gbit/s at a range of 3.5 m in non-line-of-sight environments, while up to 10 Gbit/s are feasible at more than 1 m in case of strong line of sight.

This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60 GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog-to-digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low-cost SiGe technology as two separate ICs: the 60 GHz/5 GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5 Gbit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short-range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.