11 - High-speed digital logic

Summary

Broadband serial “wireline” links today routinely reach data rates of at least 10Gb/s with the highest capacity networks, based on the OC-768 standard, running at serial data rates of 43Gb/s. At the time of writing, summer 2011, 110Gb/s links, typically achieved by aggregating four 28Gb/s serial data streams onto a single fiber, are being introduced. Even in microprocessors or ASICs, I/Os with data rates of 10Gb/s and (soon) 25Gb/s are becoming common. Despite the continued progress in CMOS I/Os, these output data rates exceed the speed capabilities of conventional static CMOS logic I/Os even in the advanced 45nm and 32nm nodes, raising the question of how such high speeds can be realized in digital networks. Instead, current-mode logic (CML), or variations thereof, is most often used in the design of very high-speed serial transmitters and receivers.

So, if CML logic is so fast, why is it only used in these high-speed applications? Why isn't this logic family used in microprocessor designs? In fact at one point it was! However, there are two main drawbacks of CML which make it unsuitable for large-scale integration. First, a CML logic gate occupies more area than its CMOS counterpart, due to the use of resistors as well as non-minimum-size transistors. The second, and more costly, drawback is the static power consumption. Even if each logic gate had a tail current of 100μA (a fairly low value for a very high-speed gate), a microprocessor with 10million gates would draw more than 1000 A. In a CMOS technology with a 1V supply, the power could exceed 1000W! Since static CMOS does not consume static current, it is much better suited for highly integrated digital ICs. Instead, CML finds use only in high-speed applications where conventional CMOS logic cannot meet the performance requirements.