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Mixed-Signal CMOS for Wireline Communication Published online by Cambridge University Press: 05 December 2024
This chapter presents systems that use a voltage-controlled oscillator in a feedback loop to lock its phase to that of a reference clock. These systems, called phase-locked loops (PLLs), generate the signals used to clock decision circuits and MUX/DEMUX circuits. An introduction to PLLs and the notion of phase comparison starts this chapter. The typical Type II analog PLL is analyzed. Split tuning and details of frequency division are presented. Digital PLLs are now commonplace necessitating an overview. Injection-locked oscillators (ILOs) play an important role as clock buffers and multiphase generators This chapter gives an overview of ILO dynamics covering topics of jitter-tracking bandwidth, lock range and injection strength.
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