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3 - Characteristics, performance, modeling, and reliability of CMOS technologies for mm-wave power amplifiers

Published online by Cambridge University Press:  05 April 2016

By
Antonino Scuderi  and
Egidio Ragonese
Edited by
Hossein Hashemi  and
Sanjay Raman
Antonino Scuderi
Affiliation:
Qualcomm
Egidio Ragonese
Affiliation:
ST-Microelectronics
Hossein Hashemi
Affiliation:
University of Southern California
Sanjay Raman
Affiliation:
Virginia Polytechnic Institute and State University
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Summary

Introduction

CMOS technology is a new player in the scenario of mm-wave technologies. Only at the beginning of the 1990s did the scientific community start to consider CMOS for RF applications and it was only at the beginning of the new millennium that aggressive dimensional scaling allowed us to figure out its exploitation at mm-waves. The dimensional scaling produced higher unity current-gain cut-off frequency (fT) and maximum oscillation frequency (fmax), at the expense of a lower breakdown voltage. Classical small-signal high-frequency building blocks (i.e. low-noise amplifiers) can manage the reduced supply voltage as the main impact is related to the available voltage dynamic. Different considerations have to be made for power amplifiers (PAs) as the inherent power performance is directly connected with the allowed voltage swing. Indeed, the generation of a 1-W power level on a 50-ohm load would require a sinusoidal voltage of 10 V (i.e. 20-vpp swing) that is not compliant with the typical breakdown voltage of submicron CMOS technologies. In order to reduce the swing on active devices, impedance transformation is needed. The problem with classical matching networks is that, when increasing the transformation ratio, very low impedance at the transistor level has to be managed. This would require a very-high-quality matching network to avoid losses [1, 2]. Passive components, mainly spiral inductors and transformers, cannot achieve very high quality factors (Q-factor), especially on CMOS conductive bulk. Silicon-on-insulator (SOI) processes can help in giving a solution for compact and high-performance integration of matching networks at the expense of higher costs.

A second basic constraint for the design of a CMOS amplifier is the gain limitation due to high input/output capacitances (i.e. intrinsic fmax limitation) and source inductive parasitics. Finally, the dimensional scaling also causes a relative increase of resistive parasitics with a direct impact on the amplifier efficiency. Indeed, since impedance transformation is related to the conversion of voltage swing into current swing, any resistive contribution would generate higher losses on high-current paths.

The nonlinear parasitics as well as the knee voltage (i.e. the voltage at which there occurs the transition from “linear” to “saturation” in the IDS-VDS characteristic) and oxide traps also impact the overall device linearity performance that is of utmost importance in modern communication systems.

Type
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Information
mm-Wave Silicon Power Amplifiers and Transmitters , pp. 77 - 138
Publisher: Cambridge University Press
Print publication year: 2016

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References

[1] I., Aoki, S., Kee, D., Rutledge, and A., Hajimiri, “A 2.4-GHz, 2.2-W, 2-V fully integrated CMOS circular-geometry active-transformer power amplifier,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), May 2001, pp. 57–60.Google Scholar
[2] I., Aoki, S., Kee, D., Rutledge, and A., Hajimiri, “Distributed active transformer: a new power combining and transformation technique,” IEEE Trans. Microwave Theory and Tech., vol. 50, pp. 316–331, Jan. 2012.Google Scholar
[3] G. D., Vendelin, A. M., Pavio, and U. L., Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques, New York: John Wiley & Sons, 1990.
[4] A., Johnson, “Physical limitations on frequency and power parameters of transistors,” IRE International Convention Record, vol. 13, pp. 27–34, Mar. 1966.Google Scholar
[5] B. G., Streetman, Solid-State Electronic Devices, Englewood Cliffs, NJ: Prentice-Hall International, Inc., 1990.
[6] S. M., Sze, Physics of Semiconductor Devices, New York: John Wiley & Sons, 1969.
[7] R. S., Muller and T. I., Kamins, Device Electronics for Integrated Circuits, New York: Wiley, 1986.
[8] S., Voinigescu, High Frequency Integrated Circuits, Cambridge University Press, 2013.
[9] Y., Taur and T. H., Ning, Fundamentals of Modern VLSI Devices, 2nd edition, Cambridge University Press, 2009.
[10] F., Stern and W. E., Howard, “Properties of semiconductor surface inversion layers in the electric quantum limit,” Phys. Rev., vol. 163, no. 3, pp. 816–835, Nov. 1967.Google Scholar
[11] T. O., Dickson et al., “The invariance of the characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks,” IEEE J. Solid-State Circuits, vol. 41, pp. 1830–1845, Aug. 206.
[12] D., Frohman-Bentchkowsky and A. S., Grove, “Conductance of MOS transistors in saturation,” IEEE Trans. Electron Devices, vol. 16, pp. 108–113, Jan. 1969.Google Scholar
[13] S. C., Cripps, RF Power Amplifiers for Wireless Communications, 2nd edition, Norwood, MA: Artech House, 2006.
[14] P. J., Tasker and B., Hughes, “Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs, IEEE Electronic Device Lett., vol. 10, pp. 291–293, July, 1989.Google Scholar
[15] P. H., Ladbrooke, MMIC Design: GaAs, FETs and HEMTs, Boston, MA: Artech House, 1989.
[16] U., Gogineni, J. A. del, Alamo, and C., Putnam, “RF power potential of 45 nm CMOS technology,” in Proc. of Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 204–207, Jan. 2010.Google Scholar
[17] C., Fager et al., “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers, IEEE J. Solid-State Circuits, vol. 39, pp. 24–34, Jan. 2004.Google Scholar
[18] M., Schwartz, Information Transmission, Modulation, and Noise, New York:McGraw-Hill, 1959.
[19] N. B., Carvalho and J. C., Pedro, “Large- and small-signal IMD behavior of microwave power amplifiers, IEEE Trans. Microwave Theory Tech., vol. 47, pp. 2364–2374, Dec. 1999.Google Scholar
[20] J., Brinkhoff, A. E., Parker, and M., Leung, “Baseband impedance and linearization of FET circuits,” IEEE Trans. Microwave Theory Tech., vol. 51, pp. 2523–2530, Dec. 2003.Google Scholar
[21] J., Brinkhoff and A. E., Parker, “Effect of baseband impedance ion FET intermodulation,” IEEE Trans. Microwave Theory Tech., vol. 51, pp. 1045–1051, Mar. 2003.Google Scholar
[22] D., Webster, J., Scott, and D., Haigh, “Control of circuit distortion by the derivative superposition method,” IEEE Microwave and Guided Wave Lett., vol. 6, pp. 123–125, Mar. 1996.Google Scholar
[23] D. R., Webster, D. G., Haigh, and A. E., Parker, “Novel circuit synthesis technique using short channel GaAs FETs giving reduced intermodulation distortion,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Apr.–May 1995, pp. 1348–1351.Google Scholar
[24] V., Aparin and L. E., Larson, “Modified derivative superposition method for linearizing FET low-noise amplifier,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 571–581, Feb. 2005.Google Scholar
[25] N. B de, Carvalho and J. C., Pedro, “Two-tone IMD asymmetry in microwaver power amplifiers,” in IEEE MTT-S Int. Microwave Symp. Dig. (IMS), vol. 1, June 2000, pp. 445–448.Google Scholar
[26] J. F., Sevic, K. L., Burguer, and M. B., Steer, “A novel envelope-termination load-pull method for ACPR optimization of RF/microwave power amplifiers,” in IEEE MTT-S Int. Microwave Symp. Dig. (IMS), vol. 2, June 1998, pp. 723–726.Google Scholar
[27] N. B. de, Carvalho and J. C., Pedro, “A comprehensive explanation of distortion sideband asymmetries,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 2090–2101, Sep. 2002.Google Scholar
[28] N., Kim, V., Aparin, and L. E., Larson, “Analysis of IM3 asymmetry in MOSFET smallsignal amplifiers,” IEEE Trans. Circuits and Systems I, vol. 58, pp. 668–676, Apr. 2011.Google Scholar
[29] C., Wang, M., Vaidyanathan, and L. E., Larson, “A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers, IEEE J. Solid-State Circuits, vol. 39, pp. 1927–1937, Nov. 2004.Google Scholar
[30] P. R., Gray and R. G., Meyer, Analog Integrated Circuits, New York: McGraw-Hill, 1994.
[31] W. B., Davenport and W. L., Root, An Introduction to the Theory of Random Signals and Noise, New York: McGraw-Hill, 1958.
[32] J. L., Lawson and G. E., Uhlenbeck, Threshold Signals, New York: McGraw-Hill, 1950.
[33] A. Van der, Ziel, Noise, New York: Prentice-Hall, 1954.
[34] J. L., Plumb and E. R., Chenette, “Flicker noise in transistors, IEEE Trans. Electron Devices, vol. 10, pp. 304–308, Sep. 1963.Google Scholar
[35] R. C., Jaeger and A. J., Broderson, “Low frequency noise sources in bipolar junction transistors, IEEE Trans. Electron Devices, vol. 17, pp. 128–134, Feb. 1970.Google Scholar
[36] M., Nishida, “Effects of diffusion-induced dislocations on the excess low-frequency noise, IEEE Trans. Electron Devices, vol. 20, pp. 221–226, Mar. 1973.Google Scholar
[37] R. A., Pucel, H. A., Haus, and H., Statz, “Signal and noise properties of gallium arsenide microwave field effect transistors,” Marton, L. (ed), Advances in Electronics and Electron Physics, Academic Press, vol. 38, pp. 195–265, 1975.
[38] H., Statz, H. A., Haus, and R. A., Pucel, “Noise characteristics of gallium arsenide fieldeffect transistor,” IEEE Trans. Electron Devices, vol. 21, pp. 549–562, Sep. 1974.Google Scholar
[39] A., Cappy, “Noise modeling and measurement techniques,’ IEEE Trans. Microwave Theory Tech., vol. 36, pp. 1–10, Jan. 1988.Google Scholar
[40] A. Van der, Ziel, “Thermal noise in field effect transistor,” Proceedings of the IRE, vol. 50, pp. 1808–1812, Aug. 1962.Google Scholar
[41] A. Van der, Ziel,“Gate noise in field effect transistors at moderately high frequencies,” Proceedings of the IEEE, vol. 51, pp. 461–467, Mar. 1963Google Scholar
[42] M., Rudolph and F., Bonani, “Low frequency noise in nonlinear systems,” IEEE Microwave Magazine, vol. 10, pp. 84–92, Feb. 2009.Google Scholar
[43] T. H., Lee and A., Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, pp. 326–336, Mar. 2000.Google Scholar
[44] J., Plá,“Characterization and modeling of high power RF semiconductor devices under constant and pulsed excitations,” in Proc. Fifth Annual Wireless Symposium, Feb. 1997, pp. 467–472.Google Scholar
[45] Q., Li, J., Zhang, W., Li, et al., “RF circuit performance degradation due to soft breakdown and HC effect in deep submicrometer CMOS technology,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 1546–1551, Sep. 2001.Google Scholar
[46] J. P., Walko and B., Abadeer, “RF S-parameter degradation under hot carrier stress,” in Proc. IEEE 42nd Annual Int. Reliability Phys. Symp., Apr. 2004, pp. 422–425.Google Scholar
[47] C., Yu and J. S., Yuan, “MOS RF reliability subject to dynamic voltage stress modeling and analysis,” IEEE Trans. Electron Devices, vol. 52, pp. 1751–1758, Aug. 2005.Google Scholar
[48] W.-C., Lin, T.-C., Wu, Y.-H., Tsai, L.-J., Du, and Y.-C., King, “Reliability evaluation of class- E and class-A power amplifiers with nanoscaled CMOS technology,” IEEE Trans. Electron Devices, vol. 52, pp. 1478–1483, July 2005.Google Scholar
[49] E., Xiao, “Hot carrier effects on CMOS RF amplifiers,” in Proc. 43rd Annual Int. Reliability Phys. Symp., Apr. 2005, pp. 680–681.Google Scholar
[50] T., Sowlati and D. M. W., Leenaerts, “A 2.4-GHz 0.18-µm CMOS self-biased cascode power amplifier,” IEEE J. Solid-State Circuits, vol. 38, pp. 1318–1324, Aug. 2003.Google Scholar
[51] C. D., Presti, F., Carrara, A., Scuderi, S., Lombardo, and G., Palmisano, “Degradation mechanisms in CMOS power amplifiers subject to radio-frequency stress and comparison to the DC case,” in IEEE Proc. International Reliability Physics Symp. (IRPS), Apr. 2007, pp. 86–92.Google Scholar
[52] S., Lombardo, J. H., Stathis, B. P., Linder, et al., “Dielectric breakdown mechanisms in gate oxides,” J. Applied Physics, vol. 98, pp. 121301–121301-36, Dec. 2005.Google Scholar
[53] A., Scuderi, T., Biondi, E., Ragonese, and G., Palmisano, Integrated Inductors and Transformers: Characterization, Design and Modeling for RF and mm-Wave Applications, Boca Raton, FL: CRC/Taylor and Francis, 2010.
[54] S. S., Mohan, M. del Mar, Hershenson, S. P., Boyd, and T. H., Lee, “Simple accurate expressions for planar spiral inductances,” IEEE J. Solid-State Circuits, vol. 34, pp. 1419–1424, Oct. 1999.Google Scholar
[55] C. P., Yue and S. S., Wong, “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, pp. 743–752, May 1998.Google Scholar
[56] F., Carrara, A., Italia, E., Ragonese, and G., Palmisano, “Design methodology for the optimization of transformer loaded RF circuits, IEEE Trans. Microwave Theory Tech., vol. 53, pp. 761–768, Apr. 2006.Google Scholar
[57] J. R., Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368–1382, Sep. 2000.Google Scholar
[58] E., Ragonese, G., Sapone, and G., Palmisano, “High-performance interstacked transformers for mm-wave ICs,” Wiley Microwave and Optical Technology Letters, vol. 52, pp. 2160–2163, Sep. 2010.Google Scholar
[59] V., Giammello, E., Ragonese, and G., Palmisano, “A transformer-coupling current-reuse SiGe HBT power amplifier for 77-GHz automotive radar,” IEEE Trans. Microwave Theory Tech., vol. 60, pp. 1676–1683, June 2012.Google Scholar
[60] E., Ragonese, G., Sapone., V., Giammello, and G., Palmisano, “Analysis and modeling of interstacked transformers for mm-wave applications,” Springer Analog Integrated Circuits and Signal Processing, vol. 72, pp. 121–128, June 2012.Google Scholar
[61] V., Giammello, E., Ragonese and G., Palmisano, “Transformer-coupled cascode stage for mm-wave power amplifiers in sub-µm CMOS technology,” Springer Analog Integrated Circuits and Signal Processing, vol. 66, pp. 449–453, Mar. 2011.Google Scholar
[62] K. T., Ng, B., Rejaei, and J. N.|Burghartz, “Substrate effects in monolithic RF transformers on silicon,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 377–383, Jan. 2002.Google Scholar
[63] T., Biondi, A., Scuderi, E., Ragonese, and G., Palmisano, “Analysis and modeling of layout scaling in silicon integrated stacked transformers,” IEEE Trans. Microwave Theory Tech., vol. 54, pp. 2203–2210, May 2006.Google Scholar
[64] E., Ragonese, A., Scuderi, T., Biondi, and G., Palmisano, “Scalable lumped modeling of single-ended and differential inductors for RF IC design,” Wiley International Journal of RF and Microwave Computer-Aided Engineering, vol. 19, pp. 110–119, Jan. 2009.Google Scholar
[65] W., Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4, New York: Wiley-IEEE Press, 2001.
[66] W., Kruppa and K. F., Sodomsky, “An explicit solution for the scattering parameters of a linear two-port measured with an imperfect test set,” IEEE Trans.Microwave Theory Tech., vol. 19, pp. 122–123, Jan. 1971.Google Scholar
[67] S., Padmanabhan, P., Kirby, J., Daniel, and L., Dunleavy, “Accurate broadband on-wafer SOLT calibrations with complex load and thru models,” in Proc. 61st ARFTG Microwave Measurements Conf. – Spring, June 2003, pp. 5–10.Google Scholar
[68] A., Ferrero and U., Pisani, “QSOLT: a new fast calibration algorithm for two port S parameter measurements,” in Proc. 38th ARFTG Microwave Measurements Conf., Dec. 1991, pp. 15–24.Google Scholar
[69] H. J., Eul and B., Schiek, “Reducing the number of calibration standards for network analyzer calibration,” IEEE Trans. Instrum. Meas., vol. 40, pp. 732–735, Aug. 1991.Google Scholar
[70] A., Ferrero and U., Pisani, “Two-port network analyzer calibration using an unknown thru,” IEEE Microwave and Guided Wave Lett., vol. 2, pp. 505–507, Dec. 1992.Google Scholar
[71] G. F., Engen and C. A., Hoer, “Thru-reflect-line: an improved technique for calibrating the dual six-port automatic network analyzer,” IEEE Trans. Microwave Theory Tech., vol. 27, pp. 987–993, Dec. 1979.Google Scholar
[72] H. J., Eul and B., Schiek, “Thru-match-reflect: one result of a rigorous theory for deembedding and network analyzer calibration,” in Proc. 18th European Microwave Conf., Sep. 1988, pp. 909–914.Google Scholar
[73] D. F., Williams and R.B., Marks, “LRM probe-tip calibrations using nonideal standards,” IEEE Trans. Microwave Theory Tech., vol. 43, pp. 466–469, Feb. 1995.Google Scholar
[74] A., Davidson, K., Jones, and E., Strid, “LRM and LRRM calibrations with automatic determination of load inductance,” in Proc. 36th ARFTG Microwave Measurements Conf., Nov. 1990, pp. 57–63.Google Scholar
[75] B., Hughes, A., Ferrero, and A., Cognata, “Accurate on-wafer power and harmonic measurements of mm-wave amplifiers and devices,” in IEEE MTT-S Int. Microwave Symp. Dig., June 1992, pp. 1019–1022.Google Scholar
[76] T., Biondi, A., Scuderi, E., Ragonese, and G., Palmisano, “Characterization and modeling of silicon integrated spiral inductors for high-frequency applications,” Springer Analog Integrated Circuits and Signal Processing, vol. 51, pp. 89–100, May 2007.Google Scholar
[77] A., Rumiantsev and N., Ridler, “VNA Calibration,” IEEE Microwave Magazine, vol. 9, pp. 86–99, June 2008.Google Scholar
[78] D. R., Root and S., Fan, “Experimental evaluation of large-signal modeling assumptions based on vector analysis of bias-dependent S-parameter data from MESFET and HEMTs,” IEEE MTT-S Int. Microwave Symp. Dig. (IMS), June 1992, pp. 61–110.Google Scholar
[79] L., Betts, “Tracking advances in pulsed S-parameter measurements,” in Microwave and RF Journal, Sep. 2007.Google Scholar
[80] J. P., Teyssier, Ph., Bouysse, Z., Ouarch, T., Peyretaillade, and R., Quere, “40 GHz/150 ns versatile pulsed measurement system for microwave transistor isothermal characterization,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 2043–2052, Dec. 1998.Google Scholar
[81] Agilent Technologies, “Agilent PNA microwave network analyzers, application note: 1408-12.”
[82] B., Noori, et al.,“Load-pull measurements using modulated signals,” in Proc. 36th European Microwave Conf., Sep. 2006, pp. 1594–1597.Google Scholar
[83] A., Ferrero, F., Sanpietro, U., Pisani, and C., Beccari, “Novel hardware and software solutions for a complete linear and nonlinear microwave device characterization,” IEEE Trans. Instrum. Meas., vol. 43, pp. 299–305, Apr. 1994.Google Scholar
[84] D., Schreurs and J., Verspecht, “Large-signal modeling and measuring go hand-in-hand: accurate alternatives to indirect S-parameter methods,” Wiley International Journal of RF and Microwave Computer-Aided Engineering, vol. 10, pp. 6–18, Jan. 2000.Google Scholar
[85] K., Bernstein and N. J., Rohrer, SOI Circuit Design Concepts, Springer, 2000.
[86] D., Wang et al., “High performance SOI RF switches for wireless applications,” in 10th IEEE Int. Conf. Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2010, pp. 611–614.Google Scholar
[87] T.-Y., Lee and S., Lee, “Modeling of SOI FET for RF switch applications,” IEEE Radio Frequency Integrated Circuits Symp. Dig. (RFIC), May 2010, pp. 479–482.Google Scholar
[88] F., Carrara, C. D., Presti, A., Scuderi, and G., Palmisano, “Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors,” Elsevier Solid-State Electronics, vol. 54, pp. 957–964, Sep. 2010.Google Scholar
[89] Y., Wu et al., “SiO2 interface layer effects on microwave loss of high-resistivity CPW line,” Microwave and Guided Wave Lett., vol. 9, pp. 10–12, Jan. 1999.Google Scholar
[90] D. C., Kerr et al., “Identification of RF harmonic distortion on Si substrate and its reduction using a trap-rich layer”, in Proc. IEEE SiRF, Jan. 2008, pp. 151–154.Google Scholar
[91] N., Planes et al., “28 nm FDSOI technology platform for high-speed low-voltage digital applications,” in Proc. IEEE International Symposium on VLSI Technology, June 2012, pp. 133–134.Google Scholar
[92] O., Weber et al., “Junction engineering for FDSOI technology speed/power enhancement,” in Proc. IEEE International Symposium on VLSI Technology, Systems, and Applications, April 2013, pp. 1–2.Google Scholar
[93] C., Fenouillet-Beranger et al., “Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates,” in Proc. IEEE International Symposium on VLSI Technology, June 2012, pp. 115–116.Google Scholar
[94] W. G., Neudeck, “An overview of double-gate MOSFETs,” in Proc. of the 15th Biennial University/Government/Industry Microelectronics Symposium, July 2003, pp. 214–217.Google Scholar
[95] M. J., Rosker, J. D., Albrecht, E., Cohen, J., Hodiak, and Tsu-Hsi, Chang, “DARPA's GaN technology thrust,” in IEEE MTT-S Int. Microwave Symp. Dig. (IMS), May 2010, pp. 1214– 1217.Google Scholar
[96] V., Hoel et al., “High-power AlGaN/GaN HEMTs on resistive silicon substrate,” IEEE Electronics Lett., vol. 38, no. 14, pp. 750–752, July 2002.Google Scholar
[97] F., Medjdoub, M., Zegaoui, B., Grimbert, et al., “First demonstration of high-power GaNon- silicon transistors at 40 GHz,” IEEE Electron Device Lett., vol. 33, pp. 1168–1170, Aug. 2012.Google Scholar
[98] E., Ballesteros, F., Perez, and J., Perez, “Analysis and design of microwave linearized amplifiers using active feedback,” IEEE Trans. Microwave Theory Tech., vol. 36, pp. 499–504, Mar. 1988.Google Scholar
[99] D., Suh and J. G., Fossum,“The effect of body resistance on the breakdown characteristics of SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 41, pp. 1063–1066, June 1994.Google Scholar
[100] S. C., Kuehne, A. B. Y., Chan, C. T., Nguyen, and S. S., Wong, “SOI MOSFET with buried body strap by wafer bonding,” IEEE Trans. Electron Devices, vol. 45, pp. 1084–1091, May 1998.Google Scholar
[101] K. K., Young and J. A., Barnes, “Avalanche-induced drain-source breakdown in silicon-oninsulator n MOSFETs,” IEEE Trans. Electron Devices, vol. 35, pp. 426–431, Apr. 1988.Google Scholar
[102] S. E., Thompson et al., “A 90 nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790–1797, Nov. 2004.Google Scholar

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