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7 - On-chip power-combining techniques for mm-wave silicon power amplifiers

Published online by Cambridge University Press:  05 April 2016

By
Tian-Wei Huang ,
Jeng-Han Tsai  and
Jin-Fu Yeh
Edited by
Hossein Hashemi  and
Sanjay Raman
Tian-Wei Huang
Affiliation:
National Taiwan University
Jeng-Han Tsai
Affiliation:
National Taiwan Normal University
Jin-Fu Yeh
Affiliation:
National Taiwan University
Hossein Hashemi
Affiliation:
University of Southern California
Sanjay Raman
Affiliation:
Virginia Polytechnic Institute and State University
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Summary

On-chip power-combining techniques

Introduction

The millimeter-wave (mm-wave) silicon power amplifier (PA) can provide a cost-effective solution for many potential commercial applications, like 60-GHz Wi-Fi, 77-GHz car radar, or the future B4G/5G 10-Gbps cellular backhaul links. The output power requirements are distance dependent from short-range Wi-Fi using 10 dBm to long-range backhaul links with more than 20-dBm output power. Design and implementation of mm-wave PAs in advanced CMOS suffer from various challenges. Most of all, the capability of a mm-wave PA to deliver watt-level output power is restricted by the low supply voltage and the limited gain performance for large-size transistors at the mm-wave frequency band. Moreover, the thick gate devices cannot be employed in mm-wave PAs due to poor gain performance. Figure 7.1 shows the decreasing trend of supply voltage of the advanced CMOS processes.

To achieve effective mm-wave power combining, the advanced CMOS processes with multiple metal layers can provide design freedom for the layout symmetry and increased metal thickness by stacking multiple metals for loss reduction. As a result, power-combining techniques play an important role in mm-wave PA design.

Over the past decade, although the industry and academia have been devoted to developing monolithic mm-wave power-combining techniques to increase the output power, the mm-wave power-combining techniques are still challenging. The objective of this chapter is to provide the necessary background, design principles of the mm-wave power-combining techniques, and various case studies for the readers.

Performance indicators

In this section, we will introduce two performance indicators and their usages in the mm-wave power-combining techniques.

Area per way (mm2)

Generally, monolithic power-combining techniques in the literature are focused on how to generate maximum output power in a minimum chip area. As shown in Fig. 7.2, the chip area of multi-way combined PAs can be increased exponentially due to complicated multi-way power splitters and combiners. On the other hand, the output power has a saturation trend of multi-way combined PAs due to the increased loss in a multi-way power combiner.

As mentioned in the foregoing section, mm-wave PAs rely on the M-way power-combining techniques to deliver the high output power. Figure 7.3 plots the trends of the chip area of the CMOS mm-wave PAs in the literature [1–23]. As we observe from Fig. 7.3, the chip area grows significantly as the number of the combiner PA-cells increases.

Type
Chapter
Information
mm-Wave Silicon Power Amplifiers and Transmitters , pp. 257 - 301
Publisher: Cambridge University Press
Print publication year: 2016

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