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50 GHz S-shaped rat-race balun with 1.4 dB insertion loss in a wafer-level chip-size package process
Published online by Cambridge University Press: 22 June 2009
Abstract
In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies a large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using a rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with a small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480×735 µm, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.4 dB and the operating frequency ranges from 40 to 61 GHz.
- Type
- Original Article
- Information
- International Journal of Microwave and Wireless Technologies , Volume 1 , Special Issue 4: European Microwave Week 2008 , August 2009 , pp. 347 - 352
- Copyright
- Copyright © Cambridge University Press and the European Microwave Association 2009