Hostname: page-component-78c5997874-s2hrs Total loading time: 0 Render date: 2024-11-10T16:30:34.002Z Has data issue: false hasContentIssue false
  • English
  • Français

Design and Reliability Assessment of Novel 3D-IC Packaging

Published online by Cambridge University Press:  09 September 2016

Y.-F. Su ,
K.-N. Chiang  and
Steven Y. Liang
Y.-F. Su
Affiliation:
Advanced Micro-system Packaging and Nano-Mechanics Research LaboratoryDeptment of Power Mechanical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan
K.-N. Chiang*
Affiliation:
Advanced Micro-system Packaging and Nano-Mechanics Research LaboratoryDeptment of Power Mechanical EngineeringNational Tsing Hua UniversityHsinchu, Taiwan
Steven Y. Liang
Affiliation:
George W. Woodruff School of Mechanical EngineeringGeorgia Institute of TechnologyAtlanta, U.S.A.
*
*Corresponding author (knchiang@pme.nthu.edu.tw)

Abstract

Core share and HTML view are not available for this content. However, as you have access to this content, a full PDF is available via the ‘Save PDF’ action button.

Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.

Keywords

Fan-out wafer-level packagingFinite element analysisLife prediction model
Type
Research Article
Information
Journal of Mechanics , Volume 33 , Issue 2 , April 2017 , pp. 193 - 203
Copyright
Copyright © The Society of Theoretical and Applied Mechanics 2017 

References

1. Moore, G. E., “Cramming more components onto integrated circuits,” Electronics, 38, pp. 114–117 (1965).Google Scholar
2. Zhang, G. Q., Graef, M. and Van Roosmalen, F., “The rationale and paradigm of “more than Moore”, ” Proceedings of the 56th Electronic Components and Technology Conference, San Diago, U.S.A. (2006).Google Scholar
3. Lau, J. H., “Evolution and outlook of TSV and 3D IC/Si integration,” Proceedings of the 12th Electronics Packaging Technology Conference, Singapore. (2010).Google Scholar
4. Hu, D. C., Lin, P. and Chen, Y. U., “A TSV-less PoP packaging structure for high bandwith memory,” Proceedings of the 65th Electronic Components and Technology Conference, San Diego, U.S.A. (2015).Google Scholar
5. Kim, J. et al., “Application of through mold via (TMV) as PoP base package,” Proceedings of the 58th Electronic Components and Technology Conference, Lake Buena Vista, U.S.A. (2008).Google Scholar
6. Brunnbauer, M. et al., “An embedded device technology based on a molded reconfigured wafer,” Proceedings of the 56th Electronic Components and Technology Conference, San Diago, U.S.A. (2006).Google Scholar
7. Meyer, T. et al., “Embedded wafer level ball grid array (eWLB),” Proceedings of the 10th Electronics Packaging Technology Conference, Singapore. (2008).Google Scholar
8. Yew, M. C. et al., “Investigation of the trace line failure mechanism and design of flexible wafer level packaging,” IEEE Transactions on Advanced Packaging, 32, pp. 390–398 (2009).Google Scholar
9. Yew, M. C. et al., “Reliability analysis of a novel fan-out type WLP,” Soldering & Surface Mount Technology, 21, pp. 30–38 (2009).CrossRefGoogle Scholar
10. Zudock, F., Meyer, T., Brunnbauer, M. and Wolter, A., “Semiconductor device,” US 809371 (2012).Google Scholar
11. Yew, M. C., Yuan, C. A., Chou, C. Y. and Chiang, K. N., “3D electronic packaging structure having a conductive support substrate,” US 7884464 (2011).Google Scholar
12. Chou, C. Y., Yew, M. C., and Chiang, K. N., “Thin stack package using embedded-type chip carrier,” TW 395318 (2013).Google Scholar
13. Coffin, L. F., “A study of the effects of cycle thermal stress on a ductile metal,” Transactions of ASME, 76, pp. 931–950 (1954).Google Scholar
14. Gektin, V., Bar-Cohen, A. and Ames, J., “Coffin-Manson fatigue model of underfilled flip-chips,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, 20, pp. 317–326 (1997).Google Scholar
15. Manson, S. S., Thermal stress and low-cycle fatigue, McGraw-Hill, New York (1966).Google Scholar
16. Engelmaier, W., “A method for the determination of ductility for thin metallic material,” Formability of Metallic Material - 2000 A. D., American Society for Testing and Materials, 753, pp. 279–295 (1982).Google Scholar
17. Engelmaier, W. “Fatigue life of leadless chip carrier solder joints during power cycling,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 3, pp. 232–237 (1983).Google Scholar
18. Liu, C. M., Lee, C. C., and Chiang, K. N., “Enhancing the reliability of wafer level packaging by using solder joints layout design,” IEEE Transactions on Components and Packaging Technologies, 29, pp. 877–885 (2006).CrossRefGoogle Scholar
19. “Temperature cycling,” JEDEC JESD22-A104-B, EIA & JEDEC Solid State Technology Association (2000).Google Scholar
20. Yew, M. C., Tsai, M., Hu, D. C., Yang, W. K., Chiang, K. N., “Reliability analysis of a novel fan-out type WLP,” Soldering and Surface Mount Technology, 21, pp.30–38 (2009).CrossRefGoogle Scholar