Hostname: page-component-745bb68f8f-mzp66 Total loading time: 0 Render date: 2025-01-15T00:23:36.457Z Has data issue: false hasContentIssue false
  • English
  • Français

Device Limitations

Published online by Cambridge University Press:  21 February 2011

Robert W. Keyes
Robert W. Keyes*
Affiliation:
IBM T. J. Watson Research Laboratory, P. O. Box 218, Yorktown Heights, NY 10598
Get access

Abstract

Packaging technology must deal with the inexorable trend of semiconductor technology towards higher levels of integration. Extrapolation of present trends suggests that chips with 100 million devices will be produced by the end of the present century. The ability of technology to miniaturize pin-outs will limit the utilization of all of these devices for purposes other than memory. This limitation plus problems of supplying power and removing heat means that chips for high-performance large systems, where the demand for pins follows a well known rule, will probably be limited to levels of integration less than 100,000. A model of large system wiring shows that large increases in the density of wires in system packages and in the rate at which heat can be removed will be needed.

Less severe limitations apply to low cost applications. No large increase in power per chip can be anticipated. However, more powerful microprocessors will become available and will need increased amounts of input-output capability.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 108 , 1987 , 3
Copyright
Copyright © Materials Research Society 1988

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1.Meindl, J., IEEE Trans. Electr. Dev. ED–31, 1555–63 (1984).Google Scholar
2.Jones, M. E., Holton, W. C., and Stratton, R., Proc. IEEE 72, 1380–1409 (1982).Google Scholar
3.Asai, S., Proc. IEEE 74, 1623–35 (1986).Google Scholar
4.Landman, B. S. and Russo, R. L., IEEE Trans. Computers EC–20, 1469–79 (1971).Google Scholar
5. For example, Chiba, T., IEEE Trans. Computers C–27, 319–25 (1978); C. T. Goddard, IEEE Trans. Components, Hybrids, Manuf. Technol. CHMT-2, 367–71 (1979); T. S. Steele, Proc. Int. Microelectronics Conference (Anaheim 1981), pp. 13–22.Google Scholar
6.Balderes, D. and White, M. L., Proc. 35th Electronic Components Conference, 351–55 (1985).Google Scholar
7.Evans, R. T., Proc. 34th Electronic Components Conference, 374–78 (1984).Google Scholar
8.Blodgett, A., Scientific American 121 (1), 86–96 (1983).Google Scholar
9.Tuckerman, D. B. and Pease, R. F. W., IEEE Electron Device Lett. EDL–2, 126–29 (1981).Google Scholar
10.Watari, T. and Murano, H., Proc. 35th Electronic Components Conference, 192–98 (1985).Google Scholar
11.Ho, C. W., et al, IBM Journal Res. Dev. 26, 286–296 (1982).Google Scholar