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Measurement of Die Stress from Packaging and Effects of Thermal Cycling

Published online by Cambridge University Press:  21 February 2011

Murray J. Robinson ,
Cliff Tsay ,
Matthew Buynoski  and
Rajendra Pendse
Murray J. Robinson
Affiliation:
National Semiconductor, 2900 Semiconductor Drive, Santa Clara, CA 95051
Cliff Tsay
Affiliation:
National Semiconductor, 2900 Semiconductor Drive, Santa Clara, CA 95051
Matthew Buynoski
Affiliation:
National Semiconductor, 2900 Semiconductor Drive, Santa Clara, CA 95051
Rajendra Pendse
Affiliation:
National Semiconductor, 2900 Semiconductor Drive, Santa Clara, CA 95051
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Abstract

During the processing and packaging of silicon integrated circuits there are many sources of die stress. Probably the least understood and controlled is the stress introduced during the die attach and molding processes. The largest packaging stresses are due to the mismatch of the thermal expansion coefficients between the leadframe and the die,and the die and the molding material. We report results obtained by monitoring the resistance changes of implanted, p-type resistors, undergoing various heat treatments with a matrix of mold and leadframe materials.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 108 , 1987 , 43
Copyright
Copyright © Materials Research Society 1988

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References

REFERENCES

[1]Schroen, Walter H., Spencer, James L., Bryan, John A., Cleveland, Robert D., Metzgor, Terry D., and Edwards, Darvin R.; “Reliability Test and Stress in Plastic Integrated Circuits”, 19th Annual Proceddings. International Reliability Physics Symposium, 1981, IEEE Catalog No. CH1619-6, pp. 81–87.Google Scholar