In this paper we present a new method for the characterization of the interface between the transparent conductive oxide (TCO) and the p doped amorphous silicon carbide layer in solar cells. The method is based on electrical capacitance measurements versus frequency in the temperature range: 20K-200K. We use Schottky diode structures (TCO-p-i-Ag) containing the p-i structure actually present in solar cells. Analysis of capacitance at different frequencies allows one to calculate an“activation energy”. Activation energy, temperature, position and shape of the capacitance step can be related to the density of states in the p type material by a model here presented. The effects of the p layer thickness and of the carbon content are investigated. A large increase of activation energy at short thickness is found, which can be related to interface damage, increasing in material with high carbon content. The technique shows an high spatial resolution and has the advantage to investigate the material as grown in the actual device.

The quantitative description of the optical phenomena occuring in a-Si:H solar cells on textured substrates is a key issue to maximize the photovoltaic conversion efficiency. A semi-empirical numerical model is proposed taking into account the scattering induced by roughness at each interface of a multilayer structure. The scattered reflected and transmitted components are added to a classical matrix treatment of specular components. For each scattering angle, a new source beam is tracked in the subsequent layers. Light polarization and interference effects are properly taken into account and the energy deposited in each layer is derived. The model is tested on various structures and on a-Si:H p-i-n solar cells by angular-resolved reflectance and transmittance measurements and photothermal deflection spectroscopy.

Hydrogenated amorphous silicon-carbon alloys (a-SiC:H) with 1.9–2.0 eV bandgaps have been grown by glow-discharge using methane as the source of carbon with high hydrogen dilution (CH4+H2) at various substrate temperatures. A thickness dependence of the properties of un-doped films is observed. The photo-electronic properties have been much improved in these undoped alloys compared to those of CH4 based films without H-dilution, however the CH4+H2 based boron doped a-SiC:H films show little improvement. Simple p-i-n single junction solar cells using improved wide-gap a-SiC:H Mayers, based on the CH4+H2 recipe and the novel carbon feedstock trisilylmethane (TSM), show high open circuit voltages and high fill factors. The cell stability under illumination has been tested. There is no correlation in degradation rates between the a-SiC:H cell efficiency and the photoconductivity of the corresponding i-layer films.

We studied the effect of high-intensity light-soaking on the quantum efficiency spectrum of textured a-Si:H solar cells. We report experimental results on the time, temperature, and soaking light intensity dependence of the quantum efficiency (QE) measured in short circuit. Under 3Wcm-2 of white light the QE saturates after 30 minutes. The QE decays little in the blue and strongly in the red. The higher the temperature of saturation, the smaller the decay of the QE.

Information about the spatial collection efficiency in a-Si:H solar cells is obtained from the Dynamic Inner Collection Efficiency (DICE) technique. With this non-destructive method single junction solar cells with efficiencies up to 10 % have been analysed under operating conditions. The influence of i-layer deposition parameters, such as the temperature and deposition time, on the spatial collection efficiency have been investigated. Deposition parameters for the i-layer have a large influence on the collection from the first 100 nm from the p+/i-interface. A higher i-layer deposition temperature or a longer deposition time results in a higher internal collection efficiency at a depth of 70 nm into the i-layer. Also results of DICE experiments on various textured TCO substrates are presented.

When a textured conductive textured oxide (CTO)-glass substrate is used for either thin single p-i-n or thin multilayer p-i-n structures, a new mode of light-induced cell degradation occurs which has been associated with enhanced shunting. In this study, triple-junction cells were examined before and after light-soaking using dark current-voltage (I-V) analysis. Two degradation mechanisms are occurring: i) The classical bulk Staebler-Wronski defect generation mechanism causes an increase in diode quality factor, ii) In cells exhibiting more as-grown shunting behavior, light-soaking greatly enhances shunting. This enhanced shunting becomes the primary mode of degradation.

Reversible incremental current steps are also seen when measuring the (I-V) characteristics on diodes with excess shunt current due to light-soaking. This is a clear indication that the increase in shunting is caused by an increase in the number of shunt pathways and not by enhancing current through existing shunts. Optical-beam-induced current (OBIC) scans show some small defect areas of reduced current responsivity that are about 5–10 urn in diameter and may not be caused by holes in the back reflector metalization. Localized accelerated light-induced degradation is measured using the OBIC scanning laser beam on small areas (5 × 10-6 cm2), and there is some evidence that these areas degrade more than areas without defects.

In this paper we present both experimental data and computer simulations of the leakage characteristics of amorphous silicon (a-Si) thin film transistors operated under time transient conditions. The transient behaviour of these devices for realistic operating conditions is often very different from their steady-state characteristics, due to the slow response of deep traps in a-Si. Our model is in good agreement with the data and realistically accounts for the time-dependent behaviour of amorphous silicon with leakage being mainly determined by a combination of fixed charge in the passivation dielectric and a distribution of surface states at the top silicon interface. We show how voltage pulses applied to the gate of a TFT affect its performance as a pixel switch in a two-dimensional array. In particular we concentrate on the effects of light and bias stressing.

The authors have investigated the mechanism for mobility improvement in a-Si:H TFTs with smooth a-Si:H/SiNx interface. SiNx surface roughness was evaluated by Atomic Force Microscope (AFM) measurement with nanometer resolution. The properties for a-Si:H initial growth layer near the a-Si:H/SiNx interface are affected by the SiNx surface roughness. By realizing a smooth SiNx surface, the properties for a-Si:H initial growth layer have been improved and high mobility TFT has been obtained. This high mobility TFT will have a great impact in application to high resolution liquid crystal displays.

An avalanche increase of the drain current for high source-drain voltage (commonly called “kink effect”) has been observed for the first time in short-channel amorphous silicon thin-film transistors, fabricated using electron-beam lithography. This effect, caused by generation mechanisms at the drain junction, has been shown to be not only field but also temperature enhanced. The Frenkel-Poole mechanism is proposed in order to explain the data.

The experimental results regarding to the effects of ultraviolet (UV) light illumination on the characteristics of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's) have been presented. The device parameters of a-Si:H TFT, such as threshold voltage, field-effect mobility, and subthreshold slope, have been degraded by electrical stress and visible light illumination, but substantially improved by UV radiation. This may be attributed to an annealing effect on the dangling-bond defects, involving a number of phonons generated by absorption of high energy UV photons in the a-Si:H TFT channel. It has been also observed that the off-current of a-Si:H TFT decreases remarkably while the on-current changes very little. From the experimental results, we report that the improved on/off current ratio of a-Si:H TFT may be achieved by UV radiation.

We have studied the effects of interface and surface on the performance of hydrogenated amorphous silicon(a-Si:H) thin film transistors. The effects of rf power, the buffer layer between the gate insulator and a-Si:H, and the surface oxidation on the performance on the a-Si:H TFTs have been investigated. By introducing suitable buffer layer, we can increase the mobility up to 2.1 cm2/Vs. The surface oxidation gives rise to the electron accumulation near the surface.

We have used remote PECVD to deposit highly-doped μc-Si films for use as gate electrodes in MOS capacitors. The flatband voltages of capacitors with different oxide thicknesses have been measured by high-frequency capacitance-voltage and have been used to determine the work function difference between an n-type μc-Si electrode and a p-type c-Si substrate. This value for ϕμs is discussed in terms of a band diagram for the stacked-gate MOS device, and is compared to the expected value.

Transient measurements of the source-drain current ISD of amorphous silicon (a-Si:H) thin film transistors are compared with the results of two dimensional simulations. In particular, we have investigated the effect of different amorphous silicon layer thicknesses on the transient response. It is found that the dynamic response of a transistor with 0.4 μm a-Si:H is significantly slower than that of a device with only 0.06 μm of a-Si:H.

We presents a new model for the series resistance of an amorphous silicon (a-Si) thin film transistor (TFT) with an inverted-staggered configuration, considering the current spreading under the source and the drain contacts as well as the space charge limited current. The calculated results of our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the relative contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which has been verified successfully by the experimental measurements.

A new narrow width effect is described for a-Si thin film transistor, TFT, having the inverted staggered structure with source and drain contacts overlapping the edge of the island passivation nitride. In this structure, where the source and drain contacts overlap the edge of the island they contact the a-Si and make a segment of channel effectively shorter. The edges thereby contribute a greater amount to the total drive current, and as width decreases, that fraction increases; what is therefore seen is a channel length effect masquerading as a width effect.

The results of measurements down to a width of 3um are given and the effective region of enhanced current is estimated. A SPICE model is presented that allows a simple representation of this effect.

Experiments have been carried out on inverted staggered amorphous silicon (a-Si:H) thin film transistors (TFTs). Depending on the voltage stressing conditions the electronic characteristics of these devices tend to shift with time [1]. To slow these changes down, and to speed up the recovery of the TFT, a lightly doped compensation or proximity recovery layer (PRL) has been placed in close proximity to the active layer of the undoped a-Si:H [2]. The effects of varying the dopant concentrations in the PRL have been studied by comparing the PRL TFTs with conventional control TFTs containing no PRL.

Normal staggered hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT) were prepared by rf plasma deposition through a three-step process. The TFTs were constituted by an a-SiN/a-Si:H structure grown on NiCr source-drain electrodes evaporated on glass substrates. The intrinsic a-Si:H active layer (Fermi level at EC-EF = 0.7 eV) was deposited from pure SiH4 rf plasma, and the insulator layer of a-SiN was grown using a high rf power plasma (200 mW/cm2) of SiH4-N2 mixture with a SiH4 fraction of 0.5 %. Ellipsometric measurements showed that a very transparent a-SiN film was grown with an abrupt interface insulator/a-Si:H. TFTs with 0.2 μm thick a-Si:H layer and 10 μm channel length have on-off current ratios of 5 104, electron field effect mobility of 1.5 cm2/V-s (dielectric constant εri ≈ 7.9), and threshold voltage around 5 V. The results are discussed in terms of low hydrogen content and low porosity of these a-SiN films prepared from silane-nitrogen.

Our experimental studies confirm that changes in a-Si Thin Film Transistors (TFTs) under voltage stress occur in the device channel and not in the contacts. We demonstrate that stressing an a-Si TFT not only shifts the device threshold voltage but can also changes the slope of the semilog subthreshold current dependence on the gate voltage. In addition, stressing can decrease the minimum leakage current. The creation of new localized states in the amorphous silicon under voltage stress qualitatively explains all these effects, while carrier tunneling and trapping in the gate insulator layer cannot by itself explain our data. At large negative gate voltages, the leakage current increases due to the holes injected into the channel. This hole current is also affected by voltage stress as can be predicted by the state creation mechanism.

In the present work, in order to discriminate the main source of instability in a-Si:H TFTs, the determination of both threshold voltage and flat-band voltage has been performed after bias-stressing the devices with different gate voltages and at different temperatures. Flat-band voltage was determined by the space-charge photomodulation technique. From the close correlation observed between the two quantities, we conclude that the predominant instability mechanism is represented by change in the gate insulator charge at and near the semiconductor/insulator interface.

The gate/source overlap distance (ΔLs) is an important factor in fabricating self-aligned TFT with passivating layer. Six types of TFT were fabricated using thin intrinsic a-Si layers such as 20 nm,50 nm and 100 nm and a n+:a-Si or a n+:μc-Si were used as the contact layer. The least required gate/source overlap distance, ΔLsC is the critical overlap where the TFT performance is not limited by the contact. This ΔLsc was determined experimentally. ΔLsC was found to be significantly affected by the intrinsic a-Si layer thickness and the ΔLsc can be small by depositing a thin intrinsic layer. The intrinsic layer thickness dependence of ΔLsC in the linear region can be explained from a existing model. However, the behavior in the saturation region suggests the need of another model, which will be discussed here. The variation of n'contact layer shown to have a small effect on ΔLsc. In order to determine appropriate ΔLs for self-alignment TFT, the magnitude of field effect mobility, threshold voltage and drain current as well as ΔLscmust be considered.