A nonlinear circuit model (NCM) with physical parameters is proposed for direct simulation of the RF characteristics of GaN high-electron-mobility transistors (GaN HEMTs) on the basis of device structure. The physical equations are used for the construction of the model in order to connect strongly the model parameters with the device/physical parameters. Hyperbolic tangent functions are used as the model equations to ensure good model convergence and rapid simulation (short simulation time). The usefulness of these equations is confirmed by technology computer aided design (TCAD) simulation. The number of model parameters for the nonlinear components (Ids, Cgs, Cgd) is reduced to 17 by using common physical parameters for modeling the drain current and capacitance. The accuracy of this model is verified by applying to GaN HEMTs. The modeled I–V and capacitance characteristics agree well with the measurement data over a wide voltage range. Furthermore, this model can be used for the accurate evaluation of S-parameters and large-signal RF characteristics.

Wireless data communication is pushing towards 60 GHz and will most likely be served by SiGe and Complementary Metal Oxide Semiconductor (CMOS) technologies in the consumer market. Nevertheless, some applications are imposing superior performance requirements on the analog frontend, and employing III-V compound semiconductors can provide significant advantages with respect to transmitter power and noise figure. In this paper, we present essential building blocks and a novel single-chip low complexity transceiver Monolithic Microwave Integrated Circuit (MMIC) with integrated antenna switches for 60 GHz communication, fabricated in a 100 nm metamorphic high electron mobility transistor (mHEMT) technology. This technology features a measured noise figure of <2.5 dB in low-noise amplifiers at 60 GHz and the realized medium power amplifiers achieve more than 20 dBm saturated output power. Integrated antenna switches with an insertion loss of less than 1.5 dB enable the integration of the transmit and the receive stages on a single chip. A single-chip transceiver with external subharmonic Local Oscillator (LO) supply for its I/Q down- and up-converter achieves a linear conversion gain in both, the Transmit (Tx) and the Receive (Rx) paths, of more than 10 dB.

This paper synthesizes protocol measurements for Ultra High Frequency (UHF) radiofrequency identification (RFID) tags’ performance. We introduce the main parameters allowing the evaluation of an inlay tag performances. We characterize all devices implemented on the test bench. We explain the different programs and all methods used for the software automation. Finally, we studied the variation of the measured parameters as a function of power, frequency, or tag orientation, both in free space and in disturbed environment through our automated test bench

This paper presents recent advances on reconfigurable reflectarrays at the University of Perugia. In particular, the activities carried out in the framework of the FP7 project ARASCOM (“MEMS and Liquid Crystal based” Agile Reflectarray Antennas for Security and COMmunication). As for ARASCOM outcomes, the purpose of the project is the design of a very large reconfigurable reflectarray controlled with micro-electro-mechanical systems (MEMS) for mm-wave imaging system at 76.5 GHz. A system with sufficient resolution to detect concealed weapons impose challenging requirements on the antenna, which shall be made of hundreds of thousands elements. The problem has been addressed by exploiting some innovative solutions and architectures that will be described in this document. In particular, the dimensioning of the reflectarray, the proposed 1-bit geometry of elementary cell, and the innovative biasing control architecture are reported together with the MEMS design and fabrication and the experimental results of a demonstrating board that validated the adopted procedure.

In this article, the development of a high-efficiency power amplifier (PA) with the inverse class-F configuration and a novel 3/4 spiral defected ground structure (DGS) is presented. The proposed DGS structure has improved rejection characteristic and its resonance frequencies are more convenient to adjust than conventional symmetric and asymmetric spiral structure. The electromagnetic-simulated result shows that the proposed circuit has improved harmonic control performance with simplified structure and less return loss than the conventional microstrip harmonic control circuit. The 3/4 spiral harmonics control circuit (HCC) can be modeled by three parallel RLC resonators. Using the proposed structure a high-performance harmonic control circuit is designed for implementing an inverse class-F PA. For comparison, two inverse class-F PAs operating at 2.4 GHz have been implemented by the microstrip HCC and the proposed HCC, respectively. According to the experiment results, the size of the proposed inverse class-F PA is reduced by 20%, the power-added efficiency and the gain are increased by 4.8% and 1.5 dB, respectively.

In this paper, problem of efficient representation of large database of target radar cross section (RCS) is investigated in order to minimize memory requirements and recognition search time, using a tree structured hierarchical wavelet representation. Synthetic RCS of large aircrafts, in the High Frequency (HF)–Very High Frequency (VHF) bands, are used as experimental data. Hierarchical trees are built using wavelet multiresolution representation and K-means clustering algorithm. Criteria used to define these hierarchical trees are described and the obtained performances are presented.

Millimeter-wave phase shifters are important components for a wide scope of applications. An analog-type phase shifter for W-band has been designed, analyzed, fabricated, and measured. The phase shifter consists of a reconfigurable high-impedance surface (HIS) controlled by micro-electromechanical system (MEMS) varactors and placed adjacent to a silicon dielectric rod waveguide. The analog-type phase shift in the range of 0–32° is observed at 75 GHz whereas applying bias voltage from 0 to 40 V to the MEMS varactors. The insertion loss of the MEMS tunable HIS is between 1.7 and 5 dB, depending on the frequency.

This paper describes existing and new criteria for comparison and optimization of non-linear power amplifiers such as RF or microwave transmitters. In addition to intermodulation, receiver noise, and losses in the transmission system, the proposed new criteria take into account efficiency or consumed power. This results in the global optimization of a combined signal-to-noise-plus-intermodulation ratio as a function of saturated or nominal power but also consumed or dissipated power. Saturated power is limited by available technology. Consumed power and dissipated power are some of the main constraints in telecommunication satellite payloads, mobile phone handsets, and RFID (Radio Frequency IDentification). Another constraint comes from the limited size of antennas, which limits the system equivalent isotropic radiated power and gain-to-temperature ratio. With the proposed criteria the designer will be able to compare different amplifier technologies and to optimize the design and operating point of each stage of a multistage amplifier or a linearizer for a given amplifier. Interference from same or other systems is also introduced in the optimization through the use of signal-to-noise-plus-IM-plus-interference ratio criteria.

A novel calibration network for patch antennas is proposed. We introduce magnetically coupled in-situ probes, which excite the fundamental patch mode. In that way, finite array effects and mutual coupling are taken into account, providing the opportunity for accurate online calibration of active antenna terminals. The specific advantages of the approach are demonstrated for linearly polarized patch antennas. Realization aspects of the multilayer antenna are discussed and the effect of some fabrication imperfections are investigated. Measured S-parameters as well as radiation simulation results of a single patch with the integrated probes are presented. Based on simulation of antenna arrays with in-situ probes the calibration accuracy is given in theory.

In this paper, micromachined devices for millimeter-wave applications at U- and V-bands are presented. These structures are designed using a rectangular coaxial line built of gold-coated SU-8 photoresist layers, where the coaxial center conductor is suspended in air by stubs. The designs include a stepped coplanar waveguide (CPW)-to-coaxial transition at 63 GHz, with an insertion loss of 0.39 dB at 67.75 GHz and a return loss better than −10 dB across the band of operation between 54.7 and 70.3 GHz. Two filters have been designed; one centered at 42 GHz with a 10% bandwidth, and another at 63 GHz with a 5% bandwidth. Measured insertion losses of 0.77 and 2.59 dB were obtained for these filters, respectively. Measured return loss lower than 13.8 dB over the passband was achieved for both designs. The structures presented in this paper involve a low-cost manufacturing process suitable to produce integrated subsystems at millimeter waves.

In this paper, the author proposes a method based on two recent evolutionary algorithms (EAS): particle swarm optimization (PSO) and differential evolution (DE) to design nonuniformly placed linear arrays of half-wavelength long dipoles. The objective of the work is to generate pencil beam in horizontal (for parallel array) and vertical (for collinear array) plane with minimum standing wave ratio (SWR) and fixed side lobe level (SLL). Dynamic range ratio (DRR) of current amplitude distribution is kept at a fixed value. Two different examples have been presented having different array alignments. For both the configurations parallel and collinear, the excitation distribution and geometry of individual array elements are perturbed to accomplish the designing goal. Coupling effect between the elements is analyzed using induced electromotive force (EMF) method and minimized in terms of SWR. Numerical results obtained from both the algorithms are statistically compared to present a comprehensive overview. Beside this, the article also efficiently computes the trade-off curves between SLL, beam width, and number of array elements for nonuniformly spaced parallel array. It featured the average element spacing versus SWR curve for nonuniformly separated arrays. Furthermore, minimum achievable SLL performances of uniformly and nonuniformly spaced parallel arrays are compared for same average spacing in the proposed work.

This paper presents the design and characterization of an active push/pull toggle RF micro-electro-mechanical systems (MEMS) switch for satellite redundancy networks. The actively controlled pull-up mechanism allows for extended restoring capabilities of the switch in case of ON-state stiction. As a proof of concept an active push/pull MEMS capacitive switch was modeled, designed, and manufactured in shunt configuration on a 50 Ω coplanar transmission line. RF measurement results show a return loss better than 15 dB in the 0.1–40 GHz range and an insertion loss better than 0.5 dB over the same range. The restoring capability of the switch was experimentally proved up to 9 h, and a predictive model was proposed for the estimation of the switch time to failure.

This paper demonstrates a highly efficient 3-stage Doherty power amplifier (PA) employing an envelope tracking (ET) technique. The ‘3-stage’ Doherty PA is the most efficient architecture for a high peak-to-average power ratio (PAPR) signal among the various Doherty PAs. However, because of the lower peaking biases than those of the ‘N-way’ Doherty PA, the proper load modulation is hard to be achieved. To get proper modulation, the peaking PAs' gate biases have been adaptively controlled using the ET technique, and the peak power and maximum efficiency characteristic along the backed-off output power region is successfully achieved. By ADS and Matlab simulations, the overall behavior of the 3-stage Doherty PA employing the ET technique has been fully analyzed. To maximize the overall efficiency of the proposed 3-stage Doherty PA, the unit PA has been designed using class F−1 PA. For verification, the amplifier is implemented using 5 W and 10 W PEP LDMOSFETs for the 802.16e mobile world interoperability for microwave access (WiMAX) at 1 GHz with a 8.5 dB PAPR. The measured drain efficiency of the proposed 3-stage Doherty PA is 55.5% at an average output power of 37 dBm, which is a 7.54 dB backed-off output power. The digital feedback predistortion (DFBPD) algorithm has been used to linearize the proposed PA considering the ET technique. After linearization, the −33.15 dB of relative constellation error (RCE) performance is achieved, satisfying the system specification. These results show that the 3-stage Doherty employing the ET technique and saturated PA is the most suitable PA for the highly efficient and linear transmitter.

A simple method for the full characterization of passive n-port microwave monolithic integrated circuit (MMIC) structures using standard two-port vector network analyzer (VNA) measurements is presented. Its main advantages are: it does not require to perform measurements from all the ports of the network, no special calibration procedure is needed, the auxiliary terminations required by the procedure can be integrated at the border of the structure under test with minimal area increase, and it can be easily implemented in commercial CAD software. The method was applied to a nine-port microstrip structure corresponding to the output power combiner and impedance matching network of an X-band MMIC high power amplifier (HPA). The full S-parameter matrix was derived from two-port measurements and compared to the circuit–as well as electromagnetic (EM)-based simulations of the structure.

This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60 GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog-to-digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low-cost SiGe technology as two separate ICs: the 60 GHz/5 GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5 Gbit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short-range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

This paper presents an overview on novel microwave micro-electromechanical systems (MEMS) device concepts developed in our research group during the last 5 years, which are specifically designed for addressing some fundamental problems for reliable device operation and robustness to process parameter variation. In contrast to conventional solutions, the presented device concepts are targeted at eliminating their respective failure modes rather than reducing or controlling them. Novel concepts of MEMS phase shifters, tunable microwave surfaces, reconfigurable leaky-wave antennas, multi-stable switches, and tunable capacitors are presented, featuring the following innovative design elements: dielectric-less actuators to overcome dielectric charging; reversing active/passive functions in MEMS switch actuators to improve recovery from contact stiction; symmetrical anti-parallel metallization for full stress-control and temperature compensation of composite dielectric/metal layers for free-standing structures; monocrystalline silicon as structural material for superior mechanical performance; and eliminating thin metallic bridges for high–power handling. This paper summarizes the design, fabrication, and measurement of devices featuring these concepts, enhanced by new characterization data, and discusses them in the context of the conventional MEMS device design.

A broadband permeability measurement method based on the full-wave electromagnetic (EM) analysis of a non-reciprocal transmission line is presented. The dispersion diagram for the first significant modes inside the ferrite loaded section of the line is obtained. The presence of magnetostatic modes generated by the magnetized ferrite inside the line is verified. Using a mode matching technique, the theoretical scattering parameters (S-parameters) of the transmission line are calculated. The full-wave analysis is validated with measurements of material properties in limit cases.

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

A four-stage distributed amplifier utilizing low-loss slow-wave shielded (SWS) transmission lines is implemented in a standard 0.13 μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The amplifier when biased in its high current operating mode of IDtotal = 46 mA (at Vdd = 2.2 V, Pdiss = 101 mW) provides a forward transmission gain of 11.3 ± 1.5 dB with a 3-dB bandwidth of 17 GHz and a gain-bandwidth product of 74 GHz. The noise figure (NF) under the same bias condition is better than 8.5 dB up to 10 GHz. The measured output-referred 1-dB compression point is higher than +2 dBm. The amplifier is also measured under low-bias condition of IDtotal = 18 mA (at Vdd = 1.15 V, Pdiss = 20.7 mW). It provides a transmission gain of 6.6 ± 1 dB, a 3-dB bandwidth of 14.8 GHz, a gain-bandwidth product of 35.5 GHz, and a NF of better than 8.6 dB up to 10 GHz. Despite using a simple four-stage cascode design, this distributed amplifier achieves very high-gain-bandwidth product at a relatively low DC power compared to the state of the art CMOS distributed amplifiers reported in the literature. This is due to the incorporation of low-loss SWS coplanar waveguide (CPW) transmission lines with a loss factor of nearly 50% of that of standard transmission lines on CMOS-grade Si substrate.