One of the most important mechanical features in microelectronic packaging is the nterface. Recent developments in modelling interfacial fracture and the easurement of interfacial toughness relevant to microelectronic packaging are discussed.

In this paper, we report recent studies on interface adhesion in flip-chip packaging. The adhesion energies of underfill interfaces found in typical flip-chip packaging pplications are characterized and presented using a racture-mechanics approach. The effects of underfill formulations and changes in polymer top-layer on PCB and chip passivation are also evaluated. The effects of underfill organosilane content, ubstrate surface chemistry and morphology, and underfill filler content are discussed in terms of fundamental mechanisms of adhesion.

As higher levels of reliability are sought, it will become increasingly important to understand the relationship between the adhesive formulation and its bonded substrate. Johnson Matthey has been addressing this need by using molecular modeling to simulate the physical effects of adhesive components on properties such as adhesion, surface spread or bleed, and underfill flow. By using a molecular modeling method as opposed to a continuum calculation, the individual components of an adhesive may be theoretically manipulated without pre-determination of properties or property effects. The potential utility of the technique lies in the prediction or confirmation of property trends when different components or processes are used. Additionally, the molecular scale helps to gain insight of the interfacial contribution to performance.

The popcorn cracking phenomenon of plastic IC packages during the reflow soldering was investigated by conducting the stress analysis of heat transfer and moisture diffusion. Vapor pressures at delaminated interfaces between the die pad and EMC(Epoxy molding compound) were calculated and mechanistic parameters such as energy release rate, stress intensity factor and phase angle were derived under various loading conditions; thermal, crack face vapor pressure and mixed loadings. It was shown that thermal loading was the main driving force for crack propagation for small cracks lengths, but vapor pressure loading played more significant role as the crack extended.

Techniques are discussed for evaluating both critical interface adhesion values as well as the sub-critical debond behavior of polymer/silicon and polymer/polymer interfaces. Sub-critical debonding behavior is expected to be most relevant in predicting the in-service lifetime of microelectronic packages. Our research characterizes the debonding of a benzocyclobutene overlayer, as well as a technologically relevant epoxy underfill/polyimide/silicon interface system. Adhesion values are measured in a double cantilevered beam (DCB) and four-point bend fracture mechanics geometries by driving a stable debond along the relevant interfaces. The effect of temperature on subcritical debonding in an underfill/polyimide interface is described. Issues of crack path selection involving the selection of microstructurally weak paths in the layered system are considered.

Under certain environmental conditions, printed wiring boards (PWB) respond to applied voltages by developing subsurface deposits of copper salts extending from anode to cathode along separated fiber / epoxy interfaces. The formation of these deposits, termed conductive anodic filaments (CAF) require high humidity (80%RH) and high voltage gradient (5V/mil). The humidity exposure during the storage environment may cause the failure in the use environment. CAF formation is enhanced by the use of certain hot air solder leveling (HASL) fluids and / or water soluble flux constituents.

In this work, two catastrophic field failures were analyzed. Both failures were related to boards produced in a manufacturing process, which included HASL. One CAF failure occurred between a component through-hole and power plane held at a potential difference of 40V with a 0.005″ nominal spacing. The other occurred on an inner layer of a multi-layer board (MLB) between a via and ground plane held at a potential difference of 320V with 0.015” nominal spacing. The nature of the CAF was analyzed using scanning electron microscopy (SEM) and energy dispersive x-ray spectroscopy (EDS). Ion chromatography (IC) was used to identify residue extracted from a failed board. The failure phenomena known as CAF poses serious longterm reliability concerns in electronic products exposed to adverse and hostile environments, especially those with closely spaced conductors.

C-4 solder bump technology is used as an interconnect method between microelectronic chips and substrates because of four unique features; excellent electrical performance, large number of connections in area arrays, small size and superb reliability in properly fabricated terminals. C-4 terminals consist of chip metallization (BLM or UBM), solder, substrate metallization and underfill, if needed. The reliability of C-4 interconnections will be described in terms of the physical interfaces in the terminal which include insulator-metal, metal-intermetallic, grain boundary and, if needed, underfill-chip/substrate/solder interfaces. Some of these interfaces are present in the as-deposited materials while others form during the solder reflow operation. Reactive UBM's such as Ti/Cu/Au form layers of intermetallic compounds such as TiCu, TiCu2 and TiCu3 and react with hydrogen ambients to form TiH2. The solder reacts with the UBM copper to form Cu3Sn and Cu6Sn5. The solder also reacts with the substrate metallization (electroless Ni-Au as an example) to form Ni3Sn2 and Ni3Sn4. Reactions with Au also occur with the formation of TiAu4 and AuSn. These reactions can cause problems not because the intermetallics are brittle (intermetallics are relatively brittle compared to the solder but they are also very strong as compared to the solder), but because of the consequences of the reactions such as, stress increase, impurity snowplow, Kirkendall voids and intermetallic spalling. Non-reactive UBM's like Cr/Cu/Au require a “phased” region between the Cr and Cu to achieve mechanical adhesion because of the absence of reaction. Proper control of these reactions will eliminate early fails that are usually planar and occur at reaction interfaces. Long term wear-out will occur during power on-off cycling when creep/fatigue cracks nucleate and grow at the grain boundaries in the solder. If underfill is used, impurity assisted crack growth at underfill to chip/substrate/solder interfaces results in increased strain on the solder and failure. Reliability models for these various failure mechanisms will be discussed as well as methods of eliminating early interfacial failures.

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

Due to its advantage in number of I/Os over other interconnection method, flip chip interconnection technology plays a key role in today's electronics packaging. Good understanding of interfacial reactions between the solder balls and under bump metallizations (UBM) is crucial in producing sound and reliable solder joints. In the present paper, several new under bump metallization (UBM) schemes using Ni or CuNi alloys as solderable layer are investigated. Cr or Ti is used as the adhesion layer. Test joint are made by reflowing eutectic Pb-Sn solder balls on UBMs and through the use of scanning electron microscopy (SEM) and micromechanical shear testing, the reliability of the UBM scheme is determined. Experimental result shows that some of the new schemes, featuring CuNi wettable layer with Cr or Ti adhesion layer produce reliable joints.

The most commonly used lead-free solders contain large amounts of tin, which makes them incompatible with the conventional Cu-based underbump metallization (UBM) schemes. The tin in the solder reacts with the copper layer of the UBM, depleting the UBM of copper and causing loss of adhesion and a weak interface. Use of new under bump metallization schemes with Ni or CuNi alloys as the solderable layer were investigated in this study. Instead of Cr, a Tibased adhesion layer was used to decrease the amount of stress in the CuNi layer. Flip chip solder joints were made in which three Sn-Bi-Ag based lead-free solders were reflowed to several UBM pads of different compositions. The resulting interfacial microstructures were examined by SEM/EDX analysis of cross-sectioned samples. The joints were also mechanically tested in fatigue and shear to assess the quality and reliability of the interface.

Flip chip interconnection of integrated circuits (IC) for packaging applications such as direct chip attachment use Pb-Sn solders as the connection between the die and the substrate. Underbump metallization is typically used to transition from the non-solderable Al bond pad on the IC to a solderable surface such as copper using traditional blanket metal deposition, photolithography and etching procedures. In this study, we report for the first time the use of a novel process for selectively depositing adherent copper directly onto aluminum thin films, eliminating the need for adhesion promoting transition layers and additional patterning steps. Utilizing copper bearing organic solutions and standard electroless and electrolytic copper plating baths, as-deposited and annealed sputter deposited Al-x%Cu (x = 0 to 2) thin films were coated with metallic copper. An increase in the organically deposited copper nucleation site density was observed with increasing copper concentration in the sputtered aluminum/copper thin films. Preliminary results using focused ion beam microscopy indicated that dissolution of the aluminum oxide surface and subsequent deposition of copper by cementation occurs in the non-conducting organic solution at sub-micron reaction lengths. Qualitative adhesion testing of samples resulted in the majority of films passing the tape test. Demonstration of the process using 50 micron diameter vias in BCB coated flip chip test vehicles from MCNC will be presented.

High temperature joints are required for packaging and assembling the emerging high temperature semiconductor devices. A technique of producing high temperature joints at relatively low process temperature is presented. The technique uses liquid-solid interdiffusion to formulate the joint and subsequent solid-state diffusion and interaction to convert the joint material into high temperature alloy. Processes have been developed using the indium-silver binary material system. Joint melting temperature higher than 700°C has been achieved while the process temperature stays below 210°C. In this development effort, the constituent element materials are deposited in multilayer structure in high vacuum to prevent oxidation. As a result, no flux is used and no scrubbing action is applied. The joints produced are examined with a scanning acoustic microscope (SAM) to evaluate the bonding quality. The joint cross-sections are studied using SEM and EDX to find the microstructure and composition. In conventional processes, the process temperature needs to exceed the alloy melting temperature in order to produce a joint. High stresses can develop due to thermal expansion mismatch among materials involved. In the present technique, the relatively low process temperature can significantly reduce the stresses. The multilayer bonding method also facilitates control of the alloy composition and the joint thickness.

Large semiconductor devices can be subject to significant mechanical stress resulting from thermal expansion mismatch between the devices and packaging materials. This stress can either cause mechanical failure or change the operational characteristics of the device. Furthermore, this stress governs the reliability of the system during use. Therefore, a complete understanding is required of the nature of stress evolution during packaging, and its time and temperature dependence during subsequent service. In the present investigation, the absolute magnitudes and spatial distributions of time-dependent thermal residual stress are measured directly by piezospectroscopic techniques. These measurements are performed with high stress (±15 MPa) and spatial (1 μm) resolution in silicon specimens attached to substrates. Measurements are performed at room temperature on 25 mm square specimens, with continuous, layered solder joints in model specimens of silicon/solder/copper. Room temperature creep relaxation is also investigated. The stress data are then analyzed according to fundamental micromechanical models.

The analysis of the mechanical behaviour of flip-chip interconections is an essential aspect of the reliability of the devices using this technique. When manufacturing them and during their operation, the interconective systems are submitted to thermal and mechanically induced stresses. By cyclic micromechanical testing and from analysis by micro Raman of singularities, we studied the mechanical response and the failure of samples, consisting of a substrate, the interconections and a chip.

Two sort of low melting point alloys were investigated, with different metallurgies for the pads, holding the interconections.

The increasing demands on solder joints have made it imperative that they perform not only their traditional role of electrical connection but also possess good mechanical integrity. One such key mechanical property is the shear strength of the solder. A number of specimen geometries can be used to evaluate the shear strength of solders, each with its advantages and limitations. This study uses a modified double lap shear geometry to measure the shear strength of the solders as a function of strain rate. It is ahown that the shear strength measured this way is truly reflective of the complex composite formed by the copper, solder and intermetallics and may be more representative of actual conditions of use rather than measurements of the shear strengths of the bulk solder. The study also uses a modified compact tension specimen to measure the fracture of the solder under combined tensile-shear loading conditions. It is shown that the solder fracture under these conditions follows the general principles of a mixed-mode fracture mechanism map.

In flip-chip packaging an underfill mixture is placed into the chip-to-substrate standoff created by the array of solder bumps, using a capillary flow process. The flow behavior is a complex function of the mixture properties, the wetting properties, and the flow geometry. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. The measured flow behavior provides evidence that both the contact angle (θ) and the suspension viscosity (μapp) vary with time under the Influence of changing flow conditions. This nonlinear fluid behavior is modeled for the flow of both model suspensions and commercial underfill materials using an extended Washburn model.

Polymer liquid crystals (PLCs) have potential applications as printed wiring board materials and in other aspects of plastic packaging. They have a number of desirable properties such as low moisture absorption, thermoplastic behavior, and low thermal expansivity. However, PLCs can have significant anisotropy in expansivity with negative expansivities in the drawing or molding direction and relatively low positive expansivities in the transverse directions. By incorporating PLCs into an engineering polymer (EP) matrix, in our case a thermoplastic polyimide (TPI), we expected to be able to control the expansivity of the resulting blend – thereby aiding in long-term service performance and reliability. Properties such as low moisture absorption, dimensional stability at elevated temperatures, good adhesion properties, and reworkability were also sought. In this paper, we report on our work to process a TPI/PLC blend and characterize the thermal properties of the blends.

An amorphous TPI was chosen over a semicrystalline one because of a thermo-irreversible cold crystallization in the latter, causing undesirable changes in the morphology and poor adhesion to metals. Our evaluations of TPIs through thermally stimulated depolarization (TSD) and temperature-modulated differential scanning calorimetry (TMDSC) reveal sub-glass transition relaxations. We have investigated the selected semicrystalline TPI + PLC pair in the entire composition range, and concluded that the narrower range, up to 30 wt. % of the PLC, is sufficient for the achievement of our objectives. The glass transition temperature Tg = 240°C of the TPI determined by DSC is unaffected by variations of the PLC concentration. The cold crystallization temperature of the semicrystalline TPI decreases with increasing PLC concentration but upon formation of the LC-rich islands this effect becomes smaller. All the blends exhibit degradation onset temperature over 520°C. The thermal conductivity of the amorphous TPI + PLC blends varies as a function of the PLC concentration. The blends show very good film formability. The addition of the PLC improves the processability of the TPI. Thermomechanical analysis (TMA) reveals that the desired control of the expansivity of the blends is also achieved by varying the PLC concentration.

Thermal performance of conventional printed circuit materials can be increased with the use of heat sinks. Even better thermal dissipation can be achieved with the use of insulated metal boards as substrates. However, this technology is limited in the number of circuit layers and the circuit density. A novel material based on transient liquid phase sintering (TLPS) was developed and used to make additive multilayer circuits on metal substrates. The partial sintering operation of the polymer-based conductive composite is akin to that of Cermet materials, but processing is at temperatures of < 250° C. A metallurgically alloyed web is formed by TLPS, providing good conductivity and stability with respect to humidity and heat exposure. An interpenetrating polymer network provides adhesion to a variety of substrates.

Photoimageable dielectrics have been used to image circuit traces (as fine as 50 μm) and vias (down to 75 μm). The conductive composite is filled into the grooves and cured to form circuits. Sequential building of circuit and via layers yields the desired planarized circuit with blind and buried solid vias throughout the multilayer structure. Metal substrates have been chosen to achieve high thermal dissipation. The thermal conductivity of the polymer-based conductive composite itself was measured to be 25 W/mK, comparable to that of solder materials. Thermally resistive adhesive interfaces have been minimized in the fabricating the structure, resulting in a high thermal dissipation, as well as high density substrate.

Rapid advances in high power electronic packaging require the development of new heat-sink/substrate materials. Advanced composites designed to provide thermal control as well as improved thermal conductivity have the potential to provide benefits in the removal of excess heat from electronic devices. Carbon-carbon (C-C)composites are under consideration for numerous electronic packaging applications. A new manufacturing process has been developed to produce high thermal conductivity (400 W/mK) C-C composites at greatly reduced cost (less than $50/lb). However, low CTE (0.25 × 10−6cm/cm °C) of C-C composites results in reduced fatigue life in chipon- board (COB) applications with silicon chips (CTE ≈ 2.6 × 10−6 cm/cm °C). A novel process was developed to convert the carbon matrix into the SiC matrix which retains the overall high composite thermal conductivity. This novel technology is well-suited for COB applications. Several types of coatings, such as CVD AIN, CVD Si and a polymer slurry-based low dielectric coating were applied to the C-SiC composite. Processing schemes were developed to produce crack-free coatings. Metallization of the dielectric coating was performed for the process integration with electronic devices. Thus, integrated substrates for power electronics were fabricated without the need of conventional metal/ceramic joining and associated high stresses. The properties of this new composite material for power electronics substrates are presented.

Thermo-mechanical stresses in MCM-D substrate are important reliability and fabrication issues. The differences in coefficient of thermal expansion (CTE) between substrate, polymer, and metal leads to complicated stress fields in multilevel interconnect structures. While the majority of reports in the literature have focused on spin-coated polyimides, this paper mainly focuses on laminated polymer dielectrics. This study uses material sets representing typical MCM-D structures to monitor the stress level in the polymer films. The substrate deflection caused by composite stresses during fabrication and thermal cycling test is determined by a curvature measurement technique. A simple analytical model which predicts a stress contribution from each individual layer during MCM-D substrate fabrication is proposed and developed by computer simulation as well. The composite stress or bowing in multilayer structures is due to the summation of each individual layer contribution. From a thermo-mechanical stress viewpoint, Ultem® thermoplastic and the epoxy thermoset adhesive exhibit quite different behaviors. In case of the epoxy thermoset adhesive, the amount of bowing increases as number of layers increases and its behavior can be predicted by an elastic model. However, in the case of the Ultem® thermoplastic adhesive, bow values become stabilized as number of layers increases because of the stress relaxation effect of the thermoplastic adhesive during lamination process above Tg of the Ultem® thermoplastic.