The effects of front-side reflective surfaces on the emissivity and temperature measurement of silicon wafers in a Rapid Thermal Processing chamber with backside heating are examined through optics modeling. Two schemes are contrasted. In (1), the pyrometry detector looks at the back-side of the wafer; in (2), it looks at the front-side of the wafer. In both cases, the temperature errors occur when the reflector's reflectivity deviates from unity. However, the error dependence on the reflector reflectivity exhibits interesting differences in these two schemes. Under the working conditions proposed in this paper, a non-ideal reflector introduces a bigger temperature error in the “backside-detector” scheme than in the “front-detector” scheme. Practical implications of these results are also discussed.

Temperature is one of the most important quantities in semiconductor manufacturing. It plays a fundamental role in many standard production techniques and especially at RTP facilities. We will give an overview on standard temperature measurement techniques associated with RTP. Their basic principles, advantages and disadvantages will be discussed with respect to explicit applications.The potential physical and technical possibilities of optical temperature measurement are outlined as well as the problems like scattering, emissivity change and irradiation by halogen lamps. An overview on practical solutions of these problems is given together with explicit examples for applications including costs and benefits of their application.

This paper discusses various commercial aspects of Rapid Thermal Processing (RTP). It provides an overview of SEMATECH's efforts to improve the manufacturing viability of RTP. Over the past several years SEMATECH, a U.S. Government/Industry consortium, has identified thermal equipment and processing needs relating to semiconductor manufacturing. It has aggressively pursued solutions to these needs through specific equipment projects. These projects include: RTP Installed Base Productivity Improvement, 0.25um RTP Tool Development, and RTP Modeling and Component Technology. Also discussed are several thermal projects which focus on the performance of more traditional tools. A comparison between RTP and a vertical furnace with model based process control and a small batch fast ramp furnace is made. A brief discussion of an RTP gate stack cluster tool project is followed by a review of future thermal processing needs, including 300mm.

Two dimensional temperature measurements of patterned wafers are presented. The measurements are made using a commercially available CCD camera operating at λ=900nm, yielding a spatial resolution of 1 pixel per mm2 and a relative accuracy of ±0.25 °C. The emissivity is determined using a reflectivity measurement made possible by the unique properties of a short wavelength arc lamp RTP chamber. The use of this measurement system for closed loop control is discussed and the application to maintaining accurate time temperature profiles independent of emissivity is described.

State of the art rapid thermal processing is able to produce a lateral thermal homogeneity which is within the inherent resolution limits of current meterology. For the most commonly used direct or indirect control methods such as multiple thermocouple measurements, rapid thermal oxidation (RTO), or rapid thermal annealing (RTA) of plain semiconductor wafers this limit is ± 2°C. As homogeneity requirements approach those limits, pattern induced non-uniformities are getting more important.

In order to achieve rapid heating and high substrate temperatures in RTP, heater and substrate are not in equilibrium and their emission spectra differ considerably. Under such circumstances laterally varying optical characteristics on the substrate itself imply thermal non-uniformities. The influence of patterns on a silicon wafer surface on the temperature uniformity is studied. Passive patterns showing interference effects were formed out of thermal oxide and Si3N4. RTO and RTA, as well as embedded thermocouples were used for temperature measurement. The data presented show that major non-uniformities due to interference effects can be reduced by restricting the energy transfer through the patterned side of the wafer. It is shown that independent top and bottom heater bank control and controlled thermal kinetics are suitable methods to reduce the pattern related process non-uniformities.

A method of estimation of wavelength-dependent emissivity of silicon wafers using thermocouple measurements is presented here. A dynamic observer and a persistent excitation of the lamps are required for convergence of the observer's estimates to the actual values of parameters for emissivity approximation. A TI designed RTP equipment and adaptive close-loop temperature control have been used to generate the required persistent excitation. Theory of emissivity estimation by this method has been developed and illustrated by experiment with this 3- zone RTP system.

In this paper we report the first NMOSFETs with elevated S/D selectively deposited by ultra high vacuum rapid thermal chemical vapor deposition (UHV-RTCVD). The deposition process included an in-situ vacuum prebake (750 °C for 10 sec) followed by selective epitaxial growth (SEG) at 800 °C. Si2H6 was used as the silicon gas source instead of the more commonly used SiH4 and SiH2Cl2 in order to achieve high growth rates at low pressure. To prevent nucleation from occurring on insulator surfaces during growth, an etching mechanism was introduced by the addition of Cl2. The gases included 100 sccm of 10% Si2H6 in H2 and 2 sccm of Cl2 at a process pressure of 24 mTorr. An epitaxial growth rate of 160 nm/min has been achieved. The final epi thickness was around 0.1 μm. The S/D junctions were formed via ion implantation into the epi. The subsequent RTA (10 sec at 950 °C) resulted in an effective junction depth about 75 nm beneath the starting Si substrate. Process and device simulations reveal the importance of maintaining a shallow LDD junction for deep submicron devices by using low temperature selective deposition. MOSFETs exhibit good subthreshold characteristics with subthreshold swing of 86 mV/dec at a drain bias of 2.5 V, and threshold variations due to charge sharing and drain-induced-barrierlowering (DIBL) were moderate for Leff down to 0.35 μm. The gate-induced junction leakage current is below 2 pA/μm at a bias of 2.5 V.

Selective deposition of SiGe alloys by rapid thermal deposition has been studied using a commercially available Rapid Thermal Chemical Vapor Deposition (RTCVD) cluster tool. The precursors used in this work were dichlorosilane and germane diluted in either hydrogen or argon. An initial characterization was performed to find the appropriate temperature and GeH4 flow ranges to deposit epitaxial layers with low surface roughness. For layers with higher germanium concentration lower deposition temperatures are required to minimize surface roughness. The effects of the dilutant gas on the deposition were examined. An H2 dilutant affects the deposition by consuming chlorine released by the SiCl2H2 and forming HCI. When Ar is used as the dilutant, more chlorine is available for other reactions that can result in etching of the silicon surface. Finally, the effects of pre-deposition treatment were determined. When compared to a wet HF dip, a gas/vapor phase HF/methanol native oxide removal treatment appears to increase the initiation time for the epitaxial deposition reaction. This is most likely due to increased fluorine termination of the surface. When a wet HF or HF/methanol native oxide removal is followed by a UV-Cl2 process, the deposition reaction initiation time is reduced. The UV-Cl2 process was also found to etch silicon through the native oxide.

In this paper, we explore selective Si epitaxy by UltraHigh Vacuum Rapid Thermal Chemical Vapor Deposition (UHV-RTCVD) using Si2H6, H2, and C12 with particular emphasis on selectivity robustness. Two key parameters considered in this study were partial pressures of Si2H6 and H2. It was found that excessive increases in either partial pressure could lead to selectivity degradation. The two mechanisms by which the observed selectivity degradation can be explained are as follows: A higher Si2H6 partial pressure provides a larger flux of Si atoms which directly influences the probability of reaching the critical nuclei size for stable nuclei formation while an increase in H2 partial pressure reduces the desorption rate of Si adatoms from the insulator surface by reducing the available Cl in the gas phase for SiC12 formation. The impact of process parameters on epitaxial defect density was also evaluated using darkfield imaging. The results clearly indicate increasing defect density upon increases in both the chlorine flow rate and the level of contamination introduced through the silicon source gas.

A novel two-stage low temperature plasma assisted deposition process, which separates interface formation from bulk film growth, was investigated for deposition of in-situ phosphorous doped microcrystalline silicon (μc-Si) thin films on SiO2 and glass substrates. We find that the bulk layer microstructure, as characterized by reflection high energy electron diffraction and Raman scattering spectroscopy, is the same whether or not a buffer layer is used. However, we find significant differences in the room temperature dark conductivity, and the dark conductivity activation energies.

The homoepitaxy of thin film silicon layers in a horizontal, atmospheric pressure RTCVD reactor is reported. The experiments were conducted in a temperature range from 900°C to 1300°C employing the precursor trichlorosilane (TCS) and the dopant trichloroborine (TCB) diluted in hydrogen. The epilayers were evaluated by Nomarski microscopy, Rutherford backscattering spectroscopy, and scanning electron microscopy (SEM). The electrical properties of the thin film were analyzed by sheet resistance and four point probe characterization methods. We propose that the responsible mechanisms for the observed growth decline at higher precursor concentration in hydrogen are due to the reaction of the gaseous HCI with the silicon surface and the supersaturation of silicon.

We report the far-infrared measurements of the electron cyclotron resonance absorption in n-type Si/Si0. 62Ge0.38 and Si0.94Ge0.06 /Si0. 62Ge0.38 modulation- doped heterostructures grown by rapid thermal chemical vapor deposition. The strained Si and Si0.94Ge0.06 channels were grown on relaxed Si0.62Ge0.38 buffer layers, which consist of 0.6 μm uniform Si0.62Ge0.38 layers and 0.5 μm compositionally graded relaxed SiGe layers from 0% Ge to 38 % Ge. The buffer layers were annealed at 800 °C for 1 hr to obtain complete relaxation. The samples had 100 Å spacers and 300 Å 2×1019 cm-3 n-type supply layers on the tops of the 75 Å channels. The far-infrared measurements of electron cyclotron resonance were performed at 4K with the magnetic field of 4 – 8 Tesla. The effective masses determined from the slope of center frequency of absorption peak vs applied magnetic field plot are 0.20 mo and 0.19 mo for the two dimensional electron gases in the Si and Si0.94Ge0.06 channels, respectively. The Si effective mass is very close to that of two dimensional electron gas in Si MOSFET (0.198mo). The electron effective mass of Si0.94Ge0.06 is reported for the first time and about 5 % lower than that of pure Si.

In the paper presented the memory effect of boron (B), phosphorus (P), and germanium (Ge) have been studied during the chemical vapor deposition of homoepitaxial Sifilms and heteroepitaxial SiGe- layers in different RTCVD equipment. The CVDprocesses were controlled by surface kinetics on Si substrates from H2, SiH4, GeH4, PH3, and B2H6 at the pressure of 2 mbar in the temperature range of 500°cC–700°C. T1e aufodoping effect from the wafer has been separated from the loading effect of the reactor. The memory effect has been shown to be small for Ge in Si and for B in Si and SiGe. However, a remarkable high memory effect has been found for P, especially in SiGe-films. There are different methods reducing the memory effect in RTCVD-reactors. In-situ gas phase etching by HCI or NF3 gives the best results in the reactors studied here. Based on the obtained results the opportunities and limitations of integrated processing of different Si and SiGe-films (e.g. complete stacks for Si/SiGe-HBT) in the same reaction chamber have been discussed.