NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 °C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 °C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

The forward voltage drop (Vf) increase observed in 4H-SiC bipolar devices such as pin diodes due to recombination-induced Shockley stacking fault (SSF) creation and expansion has been widely discussed in the literature. It was long believed that the deleterious affect of these defects was limited to bipolar devices. However, it was recently reported that forward biasing of the body diode of a 10kV 4H-SiC DMOSFET led to similar Vf increases in the body diode I-V curve as well as a corresponding degradation in the majority carrier conduction characteristics as well and this degradation was believed to be due to the creation and expansion of SSFs during the body diode forward biasing. Here we report measurements comparing the influence of similar stressing, along with annealing and current-induced recovery experiments in DMOSFETs and merged pin-Schottky diodes with the previously reported results of these experiments in 4H-SiC pin diodes. The results of these experiments provide sufficient support that the observed degradation in the majority carrier conduction characteristics is the result of SSF expansion.

High-resolution photoinduced transient spectroscopy (HRPITS) has been applied to studying defect centers controlling the charge compensation in semi-insulating (SI), vanadium-free, bulk 6H- SiC. The photocurrent relaxation waveforms were digitally recorded in the temperature range of 50 − 750 K and a new approach to extract the parameters of defect centers from the temperature-induced changes in the time constants of the waveforms has been implemented. It is based on a two-dimensional analysis using the numerical inversion of the Laplace transform. As a result, the images of spectral fringes depicting the temperature dependences of the emission rate of charge carriers for defect centers are created. Using the new procedure for the analysis of the photocurrent relaxation waveforms and the new way of the visualization of the thermal emission rate dependences, a number of shallow and deep defect levels ranging from 80 to 1900 meV have been detected. The obtained results indicate that defect structure of undoped SI bulk 6H-SiC is very complex and the material properties are affected by various point defects occupying the hexagonal and quasi-cubic lattice sites.

Double ion implanted 4H-SiC bipolar junction transistors (BJTs) are fabricated by Al and N ion implantation to the base and emitter. The current gain of 3 is obtained at the base Al concentration of 1 × ∼ 1017 /cm3. The collector current as a function of the base Gummel number suggests that double ion implanted 4H-SiC BJT operates in the intrinsic region below the emitter in the low injection level. The high base resistance restricts the base current at VBE as low as 3 V.

This paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, 10 kV 4H-SiC MPS (Merged PiN Schottky) diodes have been fabricated on a standard wafer and a low BPD (Basal Plane Dislocation) wafer, and their IV characteristics were evaluated before and after a forward bias stress, which resulted in minority carrier recombination and conductivity modulation in the drift epilayer of the diodes. After the stressing, the diode fabricated on standard wafer showed a significant increase in forward voltage drop, as well as a marked increase in leakage current, which were due to induction of stacking faults. The diode on the low BPD wafer showed very little change after the stress because the induction of stacking faults was minimized. Similar results were also observed on a 10 kV 4H-SiC DMOSFET. The results suggest that recombination-induced stacking faults are detrimental to all device types, and injection of minority carriers in majority carrier devices should be avoided at all times.

In our study, closed-core threading screw dislocations and micropipes were studied using synchrotron x-ray topography of various geometries. The Burgers vector magnitude of TSDs can be quantitatively determined from their dimensions in back-reflection x-ray topography, based on ray-tracing simulation and this has been verified by the images of elementary TSDs. Dislocation senses of closed-core threading screw dislocations and micropipes can be revealed by grazing-incidence x-ray topography. The threading screw dislocations can be converted into Frank partial dislocations on the basal planes and this has been confirmed by transmission synchrotron x-ray topography.

A low-cost alternative route for large-scale fabrication of high purity porous silicon car-bide is reported. This allows a three-dimensional arrangement of pores with adjustable pore di-ameters from several 10 nanometers to several microns. The growth of SiC is here based on a combined sol-gel and carbothermal reduction process. Therein tetraethoxysilane is used as the primary silicon and sucrose as the carbon source. We provide two different sol-gel based ways for preparation of porous SiC, obtaining either a regular porous or a random porous type. Regu-lar porous SiC with monodisperse ordered spherical pores of predefined size is obtained via liq-uid infiltration of a removable opal matrix. Whereas random porous material with polydisperse pores of an adjustable size distribution range, but without order, can be achieved via free gas phase growth. This is performed by degradation of granulated sol-gel prepared material inside a sealed reaction chamber, resulting in a SiO/CO/SiC rich gas atmosphere, which causes SiC growth inside the granulate itself. For both types doping of the initially semi-insulating porous SiC is possible either during the sol-gel preparation or via the gas phase during the following annealing procedure. As probing dopants we have used P, N, B and Al, which are well known from 'conventional' SiC. Composition and structure of the obtained material was investigated using scanning electron microscopy, X-ray diffraction, nuclear magnetic resonance and Fourier transform infrared spectroscopy.

Single-side polished silicon carbide wafers could exhibit large bow and warp due to the presence of mechanical damage on the unpolished surface. In this study, we investigated the effect of thermal annealing on the wafer bow. Two commercial-grade, double-side polished 3¡¨ 6H SiC wafers with the bow less than 5 μm were lapped using 12 μm diamond grit. One wafer was lapped on the C-face and another on the Si-face. The lapped wafers were subjected to annealing in vacuum at temperatures between 500¢XC and 2040¢XC. The wafer bow and x-ray rocking curves were measured prior to annealing and after each annealing step in order to evaluate the extent of the surface damage and degree of healing. Thermal annealing led to a decrease in the wafer bow and sharpening of the x-ray rocking curves. However, the wafer bow generated by lapping was not completely removed until annealing temperature reached ∼2000°C.

The advantages that silicon carbide (SiC) based power electronic devices offer are being realized by using prototype or experimental devices in many different power applications ranging from medium voltage to high voltage or for high temperature or high switching frequency applications. The main advantages of using SiC-based devices are reduced thermal management requirements and smaller passive components which result in higher power density. An overview of the SiC research effort at Oak Ridge National Laboratory (ORNL) and The University of Tennessee (UT) is presented in this paper.

Synchrotron white beam x-ray reticulography was used to quantitatively map the residual stress/strain in SiC wafers. The basic principle of our study is that there exists a relationship between the stress state in a crystal and the local lattice plane orientation and that this relationship can be exploited in order to determine the full strain tensor as a function of position inside the crystal. The theoretical background of the stress mapping using synchrotron white beam x-ray reticulography is introduced and it is based on the change of plane normal of the lattice plane due to the distortion associated with the residual strain. The stress mapping of a crystal region from a commercial 4H silicon carbide wafer has been studied using this technique and the results are discussed. This technique can in principle be used in any single crystal material.

The paper reviews the basics of SiC bulk growth by the physical vapor transport (PVT) method and discuss current and possible future concepts to improve crystalline quality. In-situ process visualization using x-rays, numerical modeling and advanced doping techniques will be briefly presented which support growth process optimization. The “pure” PVT technique will be compared with related developments like the so called Modified-PVT, Continuous-Feeding-PVT, High-Temperature-CVD and Halide-CVD concepts. Special emphasis will be put on dislocation generation and annihilation and concepts to reduce dislocation density during SiC bulk crystal growth. The dislocation study is based on a statistical approach. Rather than following the evolu-tion of a single defect, statistic data which reflect a more global dislocation density evolution are interpreted. In this context a new approach will be presented which relates thermally induced strain during growth and dislocation patterning in networks.

Three dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 377 to 535 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 535 K. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 50 to 5000 watts/m2 K. In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 946 MPa to 1.31GPa. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of only AlN, Al2O3, and Si3N4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will also be explored.

The control and understanding of the incorporation of nitrogen during SiC PVT continues to play an important role in SiC crystal growth. Nitrogen acts both as a dopant and an impurity depending on the growth conditions and desired resistivity. Epitaxial growth by CVD provides some insight into N incorporation in terms of the face effects, temperature, and impact of the chemical species in terms of the C/Si ratio. This paper will present experimental results showing trends regarding nitrogen incorporation during SiC PVT. Various crystal growth processes operated under constant nitrogen partial pressures were found to produce wide ranges of SiC resistivity. These effects will be analyzed in light of the process impact on gas phase elemental composition (1), crystal stress (2), dopant activation (3) and crystal defectivity (4). The goal of this paper is to provide additional insights regarding nitrogen incorporation during SiC PVT, and in turn drive towards a more holistic approach to control the resistivity of 4H n+ SiC material, based on the understanding established from SiC epitaxy technology.

A systematic study is presented of the heteroepitaxial growth of B12As2 on m-plane 15R-SiC. In contrast to previous studies of B12As2 on other substrates, including (100) Si, (110) Si, (111) Si and (0001) 6H-SiC, single crystalline and untwinned B12As2 was achieved on m-plane 15R-SiC. Observations of IBA on m-plane (1100)15R-SiC by synchrotron white beam x-ray topography (SWBXT) and high resolution transmission electron microscopy (HRTEM) confirm the good quality of the films on the 15R-SiC substrates. The growth mechanism of IBA on m-plane 15R-SiC is discussed. This work demonstrates that m-plane 15R-SiC is potentially a good substrate choice to grow high quality B12As2 epilayers.

Having superior mechanical properties, 3C-SiC is one of the target materials for power MEMS applications. Growing 3C-SiC films on Si is challenging, as there is a large mismatch in lattice parameter and thermal expansion between the SiC film and the Si substrate that needs to be accommodated, and results in high residual stress. Residual stress control is critical in MEMS devices as upon feature release it results in substantial deformation.

3C-SiC single crystalline films were deposited on 50 mm (100) and (111) Si substrates in a hot-wall CVD reactor. The film tensile residual stress was so high that it fractured on the (111) Si wafer. The resulting film thickness on the (100) Si wafer was non-uniform, having a linear profile along the growth direction. This presented a challenge of using the substrate curvature method for calculating residual stress. Finite Element Method correction was applied to the Stoney's formula for calculating the residual stress along the wafer radius. Suggestions for reducing the amount of residual stress are made.

The growth of thick silicon carbide (SiC) epitaxial layers for large-area, high-power devices is described. Horizontal hot-wall epitaxial reactors with a capacity of three, 3-inch wafers have been employed to grow over 350 epitaxial layers greater than 100 μm thick. Using this style reactor, very good doping and thickness uniformity and run-to-run reproducibility have been demonstrated. Through a combination of reactor design and process optimization we have been able to achieve the routine production of thick epitaxial layers with morphological defect densities of around 1 cm−2. The low defect density epitaxial layers in synergy with improved substrates and SiC device processing have resulted in the production of 10 A, 10 kV junction barrier Schottky (JBS) diodes with good yield (61.3%).

We present an experimental study of asymmetric wafer deformation for 3C-SiC layers grown on deliberately misorientated silicon substrates. An asymmetric curvature has been observed both on (100) and (111) oriented layers. In this work we focus on the (100) oriented samples. The curvature of the wafers is studied as a function of wafer thickness and offcut angle. We look for the correlations between the observed asymmetric strain relaxation and the layer morphology and microstructure. We claim that different defect pattern, measured along [110] and [1-10] direction can be at the origin of almost complete relaxation of mismatch strain along the offcut direction.