Wafer thinning, one of the key enabling techniques for 3D integration, is widely studied due to its impact on Si breakage strength. However, most studies only focused on the average strength, without checking the failure mechanisms. This may result in misleading conclusions and the mechanism of breakage is still ambiguous. In this paper, the mechanical strength of wafers that were thinned using different methods [rough grinding(RG), fine grinding(FE), plasma etching(PE), chemical mechanical polishing(CMP)] was evaluated statistically and through failure analysis. The results provide the industry guidance on their wafer thinning strategy. Si wafers were thinned down to 300μm by different thinning techniques: only RG; RG+FG; RG+FG+10μm CMP and RG+FG+10μm PE. Next the samples were diced into strips and the strength was tested using a 4-point bending test. The breakage strength of the dies was plotted in Weibull graphs and on wafer maps. Both RG and PE samples showed a strong bimodal distribution. On the other hand, both FG and CMP wafers showed a monomodal behaviour. This observation was unexpected and until now never reported in literature. The RG wafer has large surface grooves and is the weakest one, as expected. The bimodal distribution of the strength of RG-dies could be related to the direction of the grinding marks on the surface (along width or length of the Si strips). There is a direct correlation with the position of the dies on the wafer and the bimodal distribution. Samples with lines perpendicular to the tensile stress (along the width of the strips) are more vulnerable than the rest. The fracture on these samples propagates vertically from the ground surface, along the {110} plane. The others are stronger and break along the {111} plane. FG improves both the surface roughness and the strength compared to RG. The Weibull curve, with a monomodal behavior, shifts to a higher breakage strength, indicating that the effect of the grooves on the breakage strength is removed by FG. After CMP, the strength raises 17% compared to FG-Si due to the removal of surface roughness. Similarly, PE increases the average strength by 15% from FG. However, the Weibull plot shows that after PE, there is again a bimodal failure distribution. The weaker one falls on top of the FG distribution and the stronger one mixes up with the CMP. This indicates that although a large fraction of these samples have a similar strength as CMP, but some parts still have defects, probably local roughness related, that serve as easy initiation of fracture. This study shows that the orientation of the grinding marks plays an important role in determining the fracture plane and thus the strength. FG can efficiently remove this effect. We also showed for the first time that even after PE there is a bimodal strength distribution. Part of the dies has the same strength as the ones after CMP, but part of the population still has a lower strength.

Significant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

Establishing a cost-effective technology for the metallization of through-Si vias (TSV) is an important factor in the realization and volume manufacturing of 3D-stacked integrated circuits (3D-SIC). Cu electroplating, which is the preferred technique, should provide not only a void-free TSV fill, but also short filling time and small overburden. The duration of the plating process is a significant contributor to the overall 3D process cost, and thus needs to be minimized. The overburden, the thickness of the material deposited on the top surface of the wafer, has to be limited for compatibility with the following processing steps (e.g. chemical mechanical polishing, CMP). In this paper we report on Cu plating of TSV-s with a thin Ta film on the field. The thin Ta film is sputtered on top of the Ta barrier/Cu seed, and inhibits Cu plating outside the TSV-s. We show that the use of this Ta-cap and in situ electrochemical monitoring techniques leads to significant savings in plating and polishing time, and thus savings in manufacturing costs of 3D-stacked integrated circuits.

We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 micron on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 sec by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

Low temperature (≤400°C) growth of polycrystalline silicon (poly-Si) is carried out using plasma-enhanced chemical vapour deposition. After an initial preparation step poly-Si was grown on the substrates. Optical band gap studies of the poly-Si films have been correlated to hydrogen content of the films as well as to their photoconductivity. Furthermore, the suitability of these films for use as information storage materials for future generation 3-D flash memory devices is investigated using capacitance-voltage (C-V) measurements via metal-insulator-semiconductor device structures. C-V analysis indicates strong charge storage behavior for the poly-Si films.

Heterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Three-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed.

A typical copper-copper thermocompression bonding process is carried out in an ultrahigh vacuum (UHV) or inert environment at a bonding temperature >300°C. The ultraclean environment serves a single purpose – to maintain oxide-free copper surfaces, allowing intimate physical contact between copper atoms. This study investigates the temperature dependence of direct copper bonding from room temperature to 300°C under ambient condition. An anomalous thermal dependence of bond strength occurs between 80°C to 140°C where an increase in bonding temperature within this regime is in fact, detrimental to joint strength. This is interpreted as a thermal competition between oxidation and bond formation. This study also demonstrates that by simply coating the copper surface with a self assembled monolayer of 1-undecanethiol prior to bonding, Cu joints can be successfully formed at close to ambient temperature without a vacuum, yielding joint shear strengths on the order of 70MPa. The densely packed monolayer serves to passivate the copper surface against oxidation under ambient conditions. The ultrathin organic monolayer structure, as compared to a bulk oxide layer, could be easily displaced during the mechanical deformation at the bonding interface which accompanies thermocompression. This method could be an effective simple bonding solution for three-dimensional integrated chips.

The texture and microstructure of electrodeposited Ni layers formed in an additive-free Watt's bath were investigated. The microstructure of the electrodeposited Ni layer consists of fine columnar grains extending along the growth direction. The major texture components of electrodeposited Ni layers on Ni-P substrate were (112) and (110) fibers. On the other hand, electrodeposited Ni layers on Cu substrate had a strong (110) fiber texture. In the vicinity of the interface between the electrodeposited Ni layer and the Cu substrate, obvious epitaxial regions were not observed. Many twins parallel to the growth direction were observed in the electrodeposited Ni layer. It is suggested that grains with a twin relationship grew preferentially during the electrodeposition reaction.