This article introduces the November 2004 issue of MRS Bulletin on the state of the art in solid-state memory and storage technologies.The memory business drives hundreds of billions of dollars in sales of electronic equipment per year. The incentive for continuing on the historical track outlined by Moore's law is huge, and this challenge is driving considerable investment from governments around the world as well as in private industry and universities. The problem is this: recognizing that current approaches to semiconductor-based memory are limited, what new technologies can be introduced to continue or even accelerate the pace of complexity? The articles in this issue highlight several commercially available memories, as well as memory technologies that are still in the research and development stages. What will become apparent to the reader is the huge diversity of approaches to this problem.

In order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.

Magnetoresistive random-access memory (MRAM) is a new memory technology that is nearing commercialization. MRAM integrates a magnetic tunnel junction (MTJ) device with standard silicon-based microelectronics, resulting in a combination of qualities not found in other memory technologies. For example, MRAM is nonvolatile, has unlimited read and write endurance, and is capable of high-speed read and write operations. In this article, we will describe the fundamentals of an MTJ-based MRAM as well as recent important technology developments in the areas of magnetic materials and memory cell architecture. In addition, we will compare the present and future capabilities of MRAM to those of existing memory technologies such as static RAM and flash memory.

The current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of FeRAM called 6T4C—containing static RAM (SRAM) cells composed of six transistors (6T) and four ferroelectric capacitors (4C)—has been commercially produced. This type of FeRAM features a nondestructive readout operation, unlimited read/write cycling, and a fast access time of less than 10 ns. Lastly, the status of field-effect-transistor (FET)-type FeRAM is reviewed, emphasizing that the data retention time of a ferroelectric-gate FET has been improved to more than a month in recent studies.

Phase-change nonvolatile semiconductor memory technology is based on an electrically initiated, reversible rapid amorphous-to-crystalline phase-change process in multicomponent chalcogenide alloy materials similar to those used in rewriteable optical disks. Long cycle life, low programming energy, and excellent scaling characteristics are advantages that make phase-change semiconductor memory a promising candidate to replace flash memory in future applications. Phase-change technology is being commercialized by a number of semiconductor manufacturers. Fundamental processes in phase-change semiconductor memory devices, device performance characteristics, and progress toward commercialization of the technology are reviewed.

Recently, organic nonvolatile memory devices have attracted considerable attention due to their low cost and high performance. This article reviews recent developments in organic nonvolatile memory and describes in detail an organic electrical bistable device (OBD) that has potential for applications. The OBD consists of a tri-layer of organics/metal nanoclusters/organics sandwiched between top and bottom electrodes. A sufficiently high applied bias causes the metal nanoparticle layer to become polarized, resulting in charge storage near the two metal/organic interfaces. This stored charge lowers the resistance of the device and leads to an electrical switching behavior. The ON and OFF states of an OBD differ in their conductivity by several orders of magnitude and show remarkable bistability—once either state is reached, the device tends to remain in that state for a prolonged period of time. More important, the conductivity states of an OBD can be precisely controlled by the application of a positive voltage pulse (to write) or a negative voltage pulse (to erase). Device performance tests show that the OBD is a promising candidate for high-density, low-cost electrically addressable data storage applications.

Hybrid complementary metal oxide semiconductor (CMOS)/molecular memory devices are based on a dynamic random-access memory (DRAM) architecture, are fast, have high density, and exhibit low power consumption. These devices use a well-characterized charge storage mechanism to store information based on the intrinsic properties of molecules attached to a CMOS platform. The molecules are designed in a rational way to have known electrical properties and can be incorporated into CMOS devices with only minor modification of existing fabrication methods. Each memory element contains a monolayer of molecules (typically 100,000–1,000,000) to store charge; this process yields a structure that has many times the charge density of a typical DRAM capacitor, obviating the necessity for a trench or stacked capacitor geometry. The magnitude of voltage required to remove each electron is quantized (typically a few hundred millivolts per state), making it much easier to put molecules in a known state and to detect that state with low-power operation. Existing devices have charge retention times that are >1000 times that of semiconductors, and nonvolatile strategies based on simple modifications of existing systems are possible. All of these devices are ultimately scalable to molecular dimensions and will enable the production of memory products as small as state-of-the-art lithography will allow.

The key challenges for memories that operate at the nanoscale and that are compatible with mainstream semiconductor processing are in achieving the performance characteristics that make the integration of hundreds of millions or more of such devices feasible. The concept of harnessing a single electron or just a few electrons for memory storage is very appealing, but among the issues to address are the increased variance, smaller signal, and numerous other consequences of the reduced statistics resulting from reduced number of carriers employed. Coupling a few electrons to a transistor channel provides a structure with the power gain and the necessary current for fast memory-state detection as well as compatibility with mainstream processing. Several recent ideas, such as the use of nanocrystals and defects, and decoupling storage from the read process, provide paths to addressing the issues of power, speed, technology compatibility, and variability in these structures.We discuss several approaches to nanoscale nonvolatile silicon memory, their attributes, and the underlying materials issues, with a focus on finding the design compromises necessary to enable their manufacturability.