Antimony and B-doping superlattices were employed to study the population of Si native point defects after the formation of a TiSi2 film at 800 to 890°C. Formation of a TiSi2 film at these temperatures results in interface roughness on the order of 300 Å (root mean square). Artifacts in SIMS data arising from sputtering through such a rough interface were avoided by chemomechanical polishing of the underlying Si after chemically etching off the TiSi2 film. The resulting Si surface had a roughness of 0.7 Å. Enhancement in the diffusion of Sb and retardation in the diffusion of B over control samples without a TiSi2 film indicate a vacancy supersaturation and an interstitial undersaturation.

The secondary defect annihilation by one- and two-step titanium silicidation in SiGe layers, formed by high dose Ge implantation, has been studied systematically as a function of the Ge fluence, implantation energy, silicide thickness, and silicide process conditions. In all cases the Ti thickness was kept below 20 nm, resulting in very thin Ti silicide layers typically less than 40 nm. The silicide phase was inspected by x-ray diffraction and transmission electron diffraction. Channelling Rutherford backscattering spectrometry and transmission electron microscopy were used to follow the end of range dislocation loop annihilation as a function of the silicide process conditions. The end of range loop annealing and the influence of silicidation is presented in this paper for Ge fluences above 3×1015 cm−2 and energies ranging from 70 keV to 140 keV. A model based on loop coarsening is presented which describes the observed loop annihilation behaviour.

The redistribution of titanium during the growth of epitaxial CoSi2 from the reaction of Co(20nm)/Ti(lOnm)/Si<100> structures has been investigated. The concentration of Ti in the CoSi2 layers versus annealing temperature has been determined. Emphasis is placed on the formation of inhomogeneities in the epitaxial CoSi2 layers, and the role of Ti with respect to the thermal stability of the layers. The fundamental mechanism for the development of inhomogeneities in the epitaxial CoSi2 layers will be discussed.

Phase evolution during the annealing of Co/Ti bi-layers on (100) Si has been studied by x-ray diffraction and analytical electron microscopy. X-ray diffraction performed in situ during annealing revealed a reaction pathway involving the formation of a transient phase when epitaxial CoSi2 films were grown. Analytical electron microscopy was used to identify this phase as a spinel-related phase, isostructural with Co2TiO4. This phase grows as a result of the presence of the Ti interlayer and a small amount of oxygen from the annealing ambient. Annealing in vacuum or other purified inert gases yielded polycrystalline CoSi2 films which form via a different reaction pathway that does not involve a spinel phase. This spinel phase may serve both to reduce the native oxide from the underlying Si substrate and to control interdiffusion between Si and Co during the reaction, thereby promoting epitaxial growth.

Self-aligned silicide (salicide) formation of epitaxial CoSi2, using a Co/Ti bilayer, on linear oxide (SiO2) patterned (100)Si substrate has been investigated. Rapid thermal annealing (RTA) at 550°C resulted in the lateral encroachment of silicide in the Si under the edge of the oxide. After RTA at 900°C, even though an epitaxial CoSi2 layer was formed on the Si substrate, defects such as lateral encroachment and voids were generated under the edge of the oxide. It was found that such defects lead to device failure due to the deterioration of the gate oxide and the shallow junction.

The growth of CoSi2 layers on Si(100) by Ti-interlayer mediated epitaxy (TIME) was studied. The use of a thin (1–3nm) Ti cap, the choice of an appropriate interlayer, and the removal of a metastable reaction by-product were found important for the fabrication of uniform CoSi2 layers. High quality, pinhole-free, single crystal [100]-oriented CoSi2 layers were fabricated. Multiply-oriented formation on heavily arsenic doped Si, void formation near oxide edges, and other salicide-related issues are also discussed.

A combination of near-noble and refractory metal silicides was considered for shallow contacts to silicon in VLSI circuits [1]. The objective of the present work is to investigate formation of phases between codeposited Co-Ta film, of 150 nm thickness, and n-type silicon substrates of (100) or (111) orientation. Characterization of the specimens annealed in the temperature range of 600–1100°C was done by X-ray diffraction (XRD) and transmission electron microscopy (TEM). It was found that in addition to the silicide phases of Co and Ta, the intermetallic compound Co2 Ta was also formed. Co2 Ta appears only in the lower temperature range of about 600–800°C. At temperatures of 900–1100°C only the silicon rich phases were present. These are the low resistivity phases useful for devices. No ternary phases have been observed. Silicide formation occurs at a faster rate on (111) oriented silicon substrates.

A method is introduced to reduce substrate Si consumption of the salicide process by supplying extra Si from an amorphous Si film. Si is introduced into cobalt silicide and nickel silicide at the time when the silicide is converted into the disilicide phase. The reaction rate with amorphous Si is higher than that with single crystal Si if the amorphous Si has a low oxygen content.

Thin films of cobalt, nickel, and tungsten were sputtered on three types of silicon materials to explore their potential for use as silicides in thin film transistor technologies for active matrix liquid crystal displays. The metals were sputtered onto single-crystal, polycrystalline, and amorphous silicon. The metals were annealed in vacuum after deposition over temperatures ranging from 250°C to 750°C. The sheet resistance of the resulting silicide films was measured using a four point probe apparatus. Cobalt silicides with sheet resistance of less than 4 Ω/ were formed at 600°C. Nickel produced films with sheet resistance below 10 Ω/▪ at 350°C, though the surface was required to be vacuum-clean. In this study, tungsten did not produce silicides. Surface preparation has been found to be an important factor in tungsten and nickel silicidation.

This paper describes silicide and salicide technologies in Japan for 0.35 μm CMOS ULSIs and beyond. Polycide gate electrodes have been developed for CMOS devices from 1.0 μm to 0.35 μm design rule regime, in which Wsi2 has been used dominantly as a silicide gate material. On the other hand, silicide films are formed selectively on source/drain diffusion layers by salicide techniques, in which TiSi2 is used as a salicide material. TiSi2 is also used as a salicide material of both gate electrodes and source/drain diffusion layers for dual gate (n+/p+) CMOS. The TiSi2 thin film is formed by Ti sputtering and subsequent rapid thermal annealing. A preamorphization technique before Ti sputtering has been developed to obtain equal silicide properties on p+ and n+ diffusion layers. A high-temperature Ti sputtering technique has been developed in conjunction with pre-amorphization. CoSi2 and NiSi have also been developed as salicide materials for quartermicron CMOS and beyond.

A single-step, low temperature self-aligned CoSi2 process using Ti/Co source material has been developed for use in extreme submicrometer MOSFET applications. Ultra-thin CoSi2 films (∼ 20 nm) were obtained from a single-step RTA anneal at 550°C for 30 sec using Ti/Co source material on patterned n+ implanted (100) Si. X-ray diffraction was used to verify CoSi2 formation. Highresolution SEM and TEM examination showed the silicide to be microstructurally smooth and the devices showed no lateral growth of the silicide at the polysilicon spacer edge. Some voiding and lateral overgrowth was observed at the LOCOS isolation edge and this effect was exacerbated at higher anneal temperatures. This single-step low temperature CoSi2 process is a promising technology for deep-submicron MOSFET applications.

A thin Ti-siuicide film is widely used today as the low resistance shunt in a semiconductor chip. As the feature size in the chip shrinks to sub-quarter micron, the thin Ti-silicide film formed on such narrow lines transforms from C49 to C54 at increasing temperatures and agglomerates at decreasing temperatures, closing the process window for Ti-salicide process. In contrast, low resistivity Co-silicide thin films can be formed on narrow lines below the agglomeration temperature. In addition, an epitaxial CoSi2 with a flat interface can be formed in source/drain areas, enabling the formation of very shallow junctions with low leakage current. Experimental results on formation of silicides from Co/Ti bilayers and thermal stability of the CoSi2 films will be presented, with special emphasis on the sheet resistance of the silicide film versus poly-line width down to 0.15 umn. Interaction between dopants and silicide films will also be discussed.

Key issues associated with the self-aligned silicide technology, such as formation of silicides on narrow poly gate, shallow silicided junction formation, gate to source/drain bridging, and interface contact resistance, are discussed. The comparison of important technological aspects for TiSi2 and CoSi2 is presented. The emphasis of this work is focused on the CoSi2 salicide technology with different variations, namely conventional process, Co/Ti capping process, and Ti/Co process. Based on the experimental results, CoSi2 should be considered as an attractive alternative to TiSi2 for the applications in sub-0.25 μm ULSI integrated circuits.

Metal silicides have been used extensively in CMOS technology for reducing electrical resistance. As wafer-scale features have shrunk to the sub-half micron domain, obtaining a self-aligned silicide - or salicide - process that satisfies all requirements has become a significant challenge. One part of this challenge lies in developing the necessary scientific insights and technological innovations for the actual salicide process, while the other part lies in building a complete salicide process module which meets requirements of performance, reliability, ease of integration, control, etc. at the least possible cost and cycle-time for technology development. This second part is seldom addressed by researchers, and yet, is fundamentally important for successful application of any salicide technology to actual integrated circuit products. This paper presents a complete picture of the salicide module in the context of all the aforesaid components; and describes the use of abstraction and hierarchical models to capture process information and to facilitate process design. Prototype compact models for key wafer-state and performance outputs such as TiSi2 thickness and resistance are presented to demonstrate implementation of this process module.

Two major concerns for silicidation of ultra-shallow junctions, namely the silicon-consumption- induced junction leakage and the series resistance increase, were compared among conventional post-junction-silicide (PJS) contact, silicide-as-a-diffusion-source (SADS) contact, Silicon-On-Insulator (SOI) contact, and elevated-source-drain (ESD) contact. Even though we found that ESD contacts would be the ultimate solution for both problems, SOI and SADS contacts provide better resistance to silicon-consumption-induced series resistance increase over conventional PJS contact because both are able to maintain a high dopant concentration at the silicide/silicon interface and thus a low specific contact resistivity. While there is no junction leakage concern for SOI contact, the SADS junction is also distinguished by low leakage owing to its lack of implant damage in the silicon substrate and uniformly doped junction along the silicide/silicon interface contour. MOSFET devices with SADS source/drain were demonstrated with quarter-μm technology. Epitaxial cobalt disilicide (CoSi2) was formed using the Ti/Co bilayer technique as a diffusion source. While both ESD and SOI processes still suffer from process complexity, integration and materials issues, we conclude that SADS contacting is a promising alternative for deep submicron devices.

The application of CoSi2 in ever shrinking Si CMOS source-drain technologies demands a better knowledge of the states of stress caused by the formation of cobalt-silicides in Si. In this study the variation in local mechanical stress in the silicon substrate near arrays of polycrystalline cobalt-silicide lines was investigated by micro-Raman spectroscopy. The lines were formed by annealing Co sputtered in windows in lithographically patterned, thermal oxide coated Si wafers. The CoSi2 lines varied in width from ˜0.25 to 5.0μ, in number from 2 to 7, and in thickness from ˜ 10 to 230nm. The spacing between lines was 1 and 3 times the line width.

Trends in the Si stress between CoSi2 lines are described as a function of line width and line thickness. From the stress measured in the Si, information is obtained about the stress in the CoSi2 lines. In addition, the Si stress due to lines of primarily CoSi phase (monosilicide) is compared with the Si stress due to polycrystalline-CoSi2 (disilicide) lines.

Cross section TEM and SEM micrographs of the CoSix line morphologies are used to aid the description of the resulting stress profiles. Some theoretical modeling of the stress in the Si due to the CoSix lines is presented for comparison with the micro-Raman spectroscopy results.

A detailed in situ study of silicide reactions during rapid thermal annealing of patterned structures was performed to determine the effects of linewidth (0.2 to 1.1 μm), dopants (arsenic, boron or phosphorus) and silicon substrate type (poly-Si or <100>-Si) on the C49 to C54-TiSi2 transformation. A synchrotron x-ray source and a high speed position sensitive detector were used to collect x-ray diffraction patterns of the reacting phases on a millisecond time scale, in situ, during annealing. We demonstrate that most patterned C49-TiSi2 structures (0.2 to 1.1 μm in width, 2 to 4 μm2 in area) will incompletely transform into C54-TiSi2 during rapid thermal annealing. The C49 to C54 transformation ends at about 900°C and further annealing to higher temperatures does not force the remaining C49 to transform into C54. We also observed that the C54 formation temperature increases as the linewidth of the silicide structure decreases. These results are explained by a low density of C54 nuclei in C49 which leads to a one-dimensional growth of C54 grains along the length of the patterned lines. Finally the incorporation of a Mo implant into either poly-Si or <100>-Si before the deposition of titanium is shown to increase the percentage of C49 that transforms into C54 and also to lower the C54 formation temperature.

The kinetics of the TiSi2 C49 to C54 phase transformation in thin films on patterned deepsub- micron lines, were studied to obtain the full time, temperature and linewidth dependence of the fraction transformed during rapid thermal annealing. A Johnson-Mehl-Avrami kinetic analysis was performed, obtaining Avrami exponents of 0.8±0.2 for all sub-micron lines and 1. 9±0.2 for a 40 μm side square structure, indicating heterogeneous nucleation followed by one dimensional growth for the narrow lines, and two dimensional growth for the square structure. The activation energy, of 3.9 eV, was independent of linewidth in the sub-micron range. Transformation times increased dramatically for decreasing linewidth, as the linewidth approached the grain size of the starting C49 phase. A kinetic model based on the density of nucleation sites as a function of linewidth and C49 grain size is proposed and shown to fit the data, for samples with two different C49 grain sizes.

A simple, quasi-in situ resistivity technique was used to examine the C49 to C54 conversion kinetics of TiSi2 on sub-micron (0.2 to 1.1 μm) line structures formed in a self-aligned silicide (salicide) process. This technique was used to examine both aggregate conversion vs. time behavior and individual-line conversion vs. time behavior as a function of linewidth and polysilicon doping. As linewidth decreased, aggregate conversion vs. time at temperature behavior slowed, and the conversion behaviors shown by nominally identical lines became more variable. Four line behaviors were identified on the narrowest lines: short incubation/prompt conversion, gradual conversion, incomplete conversion, and no conversion. These behaviors are compared to those predicted by the Avrami equation, and to those predicted for a nucleation-site-density controlled reaction under conditions of low nucleation density. It is suggested that C49-C54 conversion in narrow lines may be primarily limited not by the number of C54 nucleation events, but by the presence of randomly occurring line-edge “defect” sites which slow and/or halt C54 grain growth.

The possibilities of using TiSi2 for contacts and interconnects in 0.25 μm and below design rule ICs are at present being investigated using the standard solid phase reaction (salicide) technique. Some problems still remain, such as phase transformation or dewettability over narrow lines. Over the last few years we have developed a TiSi2 selective CVD technique which is being used for 200 mm wafers in an industrial integrated cluster reactor. The system consists of two reaction chambers: one for Si epitaxy (and related alloys) and the other for TiSi2 deposition. The process sequence involves three main steps: (i) a wet chemical wafer cleaning, (ii) a selective silicon epitaxy for elevated source/drains to obtain minimum substrate consumption and (iii) the deposition of TiSi2 using the H2/SiH4 (or DCS)/TiCl4 gas system in the 650–750°C temperature range. The whole process time per wafer is shorter than 4 min. Selectivity, stoichiometric composition and resistivity of around 16 μmΩcm are obtained. The growth rate, uniformity, grain size and doping effects have been studied on single, polycrystalline, doped and undoped silicon. Device wafers have been used to compare the two processes, standard and CVD, obtaining electrical results such as lower series resistances, and a linewidth independent sheet resistance of down to 0.20 μm.