In this paper we review various methods of improving the properties of extremely thin dielectrics (<20 nm) using a nitrogen rich environment. The three main gases considered being ammonia, and nitrous and nitric oxides. We present original results for nitric oxide exposed silicon and suggest that for ultra thin dielectric (<5 nm) that these layers are generally superior to any others, whilst for thicker layers oxides annealed in nitrous oxides appear to display the best properties.

A study comparing the oxide growth and electrical properties of 60Å oxides grown in different mixtures of O2 and N2O was performed. The oxide growth for all mixtures examined, as well as that of the pure O2 and N2O cases, fit a Deal-Grove oxidation model modified for Rapid Thermal Oxidation (RTO). Linear growth rate constants found for both a simple linear model and the modified Deal-Grove model are significantly greater for mixtures containing only 35% O2 than for pure N2O oxidation. The uniformity of the oxide growth across the wafer for the gas mixtures resembles that seen in pure N2O oxidation rather than pure O2 oxidation. The electrical properties were measured using Surface Photo-Voltage (SPV) techniques along with conventional Capacitance-Voltage (C-V) and Current-Voltage (I-V) techniques. Oxides grown in 100% N2O showed significantly higher oxide charge when compared to oxides grown in 100% O2. An in-situ anneal in an Ar ambient reduces the oxide charge for all gas mixtures examined. The higher oxide charge accompanies an increase in the interface trap density for the oxides grown in 100% N2O. The in-situ anneal reduces the interface trap density for oxide grown in 100% O2 but has little effect for oxides grown in 100% N2O. The interface trap density is reduced by the in-situ annealing for oxides grown in mixtures of O2 and N2O.

We have used a combination of plasma and rapid thermal processing for the formation of thin gate-dielectric films. The bulk dielectric films investigated include silicon oxide, oxynitride and multilayer oxide-nitride-oxide heterostructures formed by plasma-assisted oxidation, remoteplasma-enhanced chemical-vapor deposition (remote-PECVD) followed by post-deposition rapid thermal annealing (RTA). Auger electron spectroscopy (AES) and infrared absorption spectroscopy (IR) have been used to study the chemistry of interface formation and the bulk dielectric chemical bonding, respectively. Electrical characterization of MOS capacitor structures incorporating these dielectrics was performed by conventional capacitance and current voltage techniques, C-V and I-V, respectively.

We present recent results obtained in thin gate oxides. These oxides are grown in a new clusterable RTP-system for 200mm diameter wafers. The main innovations of the reactor are dealing with the chamber geometry, gas distribution, double pyrometry and dedicated circular lamp array in order to insure an optimized light flow onto the wafer. Analytical and electrical data are given according to several oxidant and nitridant ratios (O2, N2O), The influence of different process parameters such as temperature, reaction time, N-content are discussed.

In this paper, a detailed study is presented for the growth kinetics of rapid thermal oxidation of lightly-doped silicon in N2O and O2 on (100), (110), and (111) oriented substrates. It was found that (110)-oriented Si has the highest growth rate in both N2O and dry O2, and (100) Si has the lowest rate. There is no “crossover” on the growth rate of rapid thermal N2O oxidation between (110) Si and (111) Si as compared to oxides grown in furnace N2O. Pressure dependence of rapid thermal N2O oxidation is reported for the first time. MOS capacitor results show that the low-pressure (40 Torr) N2O-grown oxides have much less interface state generation and charge trapping under constant current stress as compared to oxides grown in either 760 Torr N2O or O2 ambient.

To meet the stringent demands of high quality gate performance in advanced devices, a more robust gate dielectric is needed. A stacked structure consisting of thermal oxide and deposited oxide is a potential candidate since it offers certain advantages over single layer oxides such as 1) reduced defect density, 2) reduced stress at the SiO2/Si interface due to stress compensation between the thermal and the deposited oxide, 3) less silicon consumption and 4) reduced thermal budget. In this study, stacked oxides consisting of RTO and RTCVD oxides are characterized. In contrast to other studies which use conventional LPCVD methods to form the top oxide, these stacked oxides have the advantages of rapid thermal and in-situ processing, which produces excellent bulk and interfacial properties. Electrical characterization has shown that these stacked oxides have superior performance compared to single layer furnace or deposited oxides.

Ultrathin silicon nitride capacitors were fabricated using in-situ multiprocessing technology. In this paper we present comparative studies of capacitor formation using standard furnace processing, rapid thermal processing (RTP), and cluster tool processing of ONO dielectric films. We show that, due to better interface control using cluster tool processing, higher capacitance can be obtained for a fixed leakage level for the same thickness of dielectric film when compared to furnace and rapid thermal processing. We discuss the structural and electrical properties of these films and show that, due to an oxide-free interface, the improved film quality results in lower leakage current density and higher reliability.

Metalorganic chemical vapor deposition (MOCVD) is an ideal technique for the deposition of conducting and non-conducting oxide based thin film materials. In this paper we present our study of RIP assisted MOCVD for the low temperature deposition of a number of oxide based advanced materials which are useful for the development of the next generation of microelectronic and optoelectronic devices. We have designed several experiments to understand the role of photoeffects in RIP assisted MOCVD. The vacuum ultraviolet, ultraviolet and visible (λ ≤ 0.7–0.8μm) photons can have several beneficial effects including the enhancement of the surface reactions of the absorbed molecules through the perturbation of the electronic state of binding between the absorbed molecules and the solid surface. We have shown a direct relationship between the structural and electrical characteristics of the deposited oxide and the spectral contents of the energy source.

The Growth of ultrathin oxides in N2O ambient has been a subject of extensive research for submicron CMOS technology. Oxides grown in N2O tend to have a higher charge-to-breakdown, less charge trapping under constant current stress, and less interface state generation under current stress and radiation than conventional oxides grown in oxygen [1,2]. In addition the penetration of boron through N2O oxides is significantly less than through conventional thermal oxides [3]. The improved characteristics of N2O are due to an interfacial pileup of nitrogen atoms [1-3]. Thus the growth of thermal oxides in N2O provides a method for obtaining many of the more favorable aspects of reoxidized-nitrided silicon dioxides, with a much simpler process.

The implementation of a wet oxidation process in an RTP system using a bubbler with deionized water is described. A special process related calibration in a wet atmosphere, by means of pyrometer and thermocouple readings, allows one to improve the temperature accuracy during the oxidation to an offset of only + 1 to 2°C. High oxide growth rates, up to a factor of 1.8 above literature data have been achieved. Wet and dry RTO oxides are compared and related to the expectations from growth models. Effects of growth time (10 s to 4 min), growth temperature (675°C-950°C), substrate orientation (100,111), preparation (e.g. HF) and bubbler temperature (20°C-90°C) are presented. The uniformity of oxides on 4 and 6 inch diameter wafers are discussed. Preferentially by the use of a silicon guard ring and by adjusting lamp power and gas flow rates excellent results concerning uniformity (standard deviations 2σ: 1-2 %) and reproducibility (variation of 0.5 to 0.75 % at least over 12 wafers) are obtained.

The insertion of single-wafer thermal and CVD technologies into the front- and back-end of the line processing starts with study of the integrated circuits manufacturing and device performance requirements. Relying upon the lessons learned and using the concurrent engineering approach, next generation processing equipment design architecture is then defined. In order to meet the process performance, throughput, and cost of ownership requirements of semiconductor IC manufacturing as defined in the SIA road map, heavy emphasis must be put on sensor fusion and model-based process control. In the existing semiconductor IC manufacturing equipment, process control is usually accomplished by control of equipment settings, qualification wafer runs and ex-situ measurements of the various wafer properties, as well as design architecture for stable equipment performance. The conventional approach, however, suffers from slow drifts of various equipment state parameters such as infrared absorbing quartz media causing thermal memory effects, or deposition of films on the reactor walls causing variation in the optical characteristics of the reactor as well as chemical and particle memory effects. Using model-based real-time control in conjunction with implementation of various in-situ and ex-situ sensors, these effects can be well monitored and controlled. This paper is to discuss various production related issues with single-wafer thermal and CVD technologies.

In this paper, we report in-situ oxygen removal on Si using SiH2Cl2 and H2 in a high vacuum rapid thermal chemical vapor deposition reactor. The system consists of a main process chamber and a load-lock with base pressures of ∼ 1×10−7 Torr and 1×10−5 Torr respectively. The experiments were conducted in the temperature range of 750°C to 865 °C, and SiH2Cl2/H2 flow ratios of 1% to 7%. For comparison, samples were also prepared with only H2 prebaking in the same temperature and pressure range as well as with no in-situ cleaning. With no in-situ cleaning, the oxygen content was found to decrease at higher temperatures suggesting partial oxygen removal during early stages of growth. The results indicate a strong temperature dependence for the H2 clean with an increased effectiveness at higher temperatures which is believed to be due to temperature dependence of oxygen desorption from Si. In the temperature range studied, the SiH2Cl2 clean was found to be effective at 750°C. An additional oxygen removal mechanism appears to be introduced by the addition of SiH2Cl2. Using this approach, at 750°C, the peak oxygen concentration can be reduced to 4×1018 cm−3 whereas the H2 anneal at the same temperature results in a concentration of 6×1018 cm−3. At higher temperatures, the oxide can be removed in pure H2 just as efficiently or desorbed during initial stages of growth. The results show that the efficiency of the process increases as more SiH2 Cl2 is added to the system up to a critical pressure. However, if the SiH2Cl2 partial pressure is above this critical value, Si deposition can occur on the Si surface yielding an optimum partial pressure which is a function of temperature. The results indicate that the use of a small amount of SiH2Cl2 as a cleaning agent may provide a low temperature pre-epi clean.

Integrated processes for IC manufacturing are today of prime importance for obtaining such high performance results as uniformity on large diameter wafers, reproducibility, throughput and reliability. Using an industrial integrated cluster reactor we have obtained selective epitaxial Si and selective TiSi2 deposition. This is a 200 mm reactor in which epitaxial silicon has been obtained with <1% (1σ) thickness uniformity and <2% over a 25 wafer batch. Full selectivity of Si on oxide has been obtained below a 20 Torr working pressure using the DCS/H2 gas system. No loading effect has been detected. The main characteristics of this system are described with the most relevant results like: sharp interfaces obtained in Si0.7Ge0.3/Si multilayer structures grown at 650°C, abruptly doped epitaxial layers and residual defect density.

TiSi2 has been selectively obtained with minimum substrate consumption using the H2/SiH4 (or DCS)/TiC14 chemistry. The elevated source & drain has also been successfully tested by selective Si epitaxy followed by “in situ” selective TiSi2 deposition to compensate for substrate consumption.

We have grown dilute Si-C epitaxial layers on Si (100) substrates at 800°C with a RTCVD process using SiH4 and C3H8. C atoms can be kinetically stabilized in interstitial sites in the Si lattice at relatively high temperatures if process parameters, such as growth rate and C/Si flux ratio, are optimized.

Passivation of III-V semiconductor surfaces and especially the GaAs surface has been studied for over two decades without significant breakthrough. However, III-V device performances are still often limited by surface properties. In particular field effect behaviour in GaAs has been impossible to obtain due to the Fermi level pinning at the surface of this material. This paper presents an integrated sequence of low thermal budget processes to provide contamination control at the GaAs surface leading to very promising field effect on GaAs.

In-situ surface cleaning using a Distributed Electron Cyclotron Resonance Microwave plasma (DECR MMP) has been integrated with a thin dielectric film deposition facility using light assisted CVD technics. Photoluminescence results carried out on GaAs surfaces have demonstrated that exposure to a hydrogen plasma induces lower recombination rates on these surfaces. Bulk diffusion of hydrogen during this process can be controlled and eliminated using an integrated Rapid Thermal Annealing (RTA). Finally, in-situ encapsulation by a dielectric allows one to stabilize the electronic properties of the surface for passivation applications. A silicon nitride film deposited by a direct UV photolysis deposition process has been developed for this study and is presented here.

This paper will present an overview of rapid thermal processing (RTP) technologies for fastcycle-time IC production. RTP has experienced significant advances in equipment design, process control capabilities, and unit process applications over the past eight years. The Microelectronics Manufacturing Science and Technology (MMST) program at TI successfully demonstrated CMOS IC production in a single-wafer factory with all-RTP thermal fabrication for various anneals, oxidations, and chemical-vapor depositions. The use of RTP in conjunction with other single-wafer processes enabled 0.35 µm IC fabrication with a 3-day cycle time. Selected RTP equipment, sensor, and process control developments will be reviewed. The RTP applications and requirements for state-of-the-art and future IC technologies will be described.

With decreasing device geometry to below sub micron dimensions, there is a greater emphasis on reducing the thermal budget by shortening and/or eliminating high temperature processing steps. The use of RTP for borophosphosilicate glass (BPSG) fusion/reflow process, which is conventionally performed in diffusion furnaces in temperature range of 850-900 °C, has gained some acceptance in recent years. BPSG films were prepared by an atmosphericpressure chemical vapor deposition(APCVD) process. BPSG film properties such as stress, shrinkage, dopant uniformity and surface stability, step coverage, and flow angle, have been examined as a function of densification/reflow cycle. We used RTP-only, furnace-only, and RTP/furnace reflow annealing cycles. The impact of various BPSG fusion scenarios on underlying Ti salicide and P-channel and N-channel devices is discussed.

Recrystallization of amorphous silicon has been investigated using conventional furnace annealing, incoherent light-based rapid thermal annealing (RTA) and pulsed laser annealing using excimner laser (wavelength=248 nm, energy density = 0.1−0.6 J/cm2) at a pulse width of approximately 20 nanoseconds. The effects of annealing methods are characterized for grain growth and crystallized orientation using transmission electron microscopy (TEM) and X-ray diffraction analysis. The various recrystallization methods are compared based on the structural properties of the resulting film and optimized thermal budgets for each heating mechanism are discussed.

The reliable operation of a dynamic random access memory (DRAM) device requires a minimum level of charge to be stored in the capacitor. The nonlinear dependence between the scaling of the minimum charge and the cell area for higher DRAM densities is the driving force in the development of exotic capacitor structures and advanced cell dielectric materials. The conventional option of reducing the thickness of the silicon nitride dielectric films for high density DRAM applications will eventually be constrained by the increase in the leakage current due to direct carrier tunneling or by the decrease in the oxidation resistance of the films.

In this paper we discuss the use of rapid thermal processing to modify the interface between the polysilicon storage node of the capacitor and the silicon nitride to improve the electrical and structural characteristics without any loss in capacitance. The influence of electrode roughness on the electrical behavior will also be discussed for the various dielectric stack combinations.

A comparison study of the effectiveness of in-situ vapor/gas phase cleaning versus conventional wet RCA based cleaning has been performed. The effectiveness of the cleans were compared using Surface Photo-Voltage (SPV) measurements of the quality of a 70Å gate dielectric. Dielectrics grown in oxygen by Rapid Thermal Oxidation (RTO) were measured using SPV. The vapor/gas phase cleaning processes studied have three steps corresponding to the baths in a conventional RCA-based clean. A clean using O2 was used to clean the organic contaminants normally cleaned in the SC-1 bath, a C12 based step corresponded to the SC-2 solution, and an HF/alcohol etch was used to remove the oxide normally etched using buffered HF. It was seen that temperature control of the cleaning chamber walls is necessary to insure reproducible processes and reasonable pump down times. Measurements by SPV indicate that dielectrics grown after vapor-gas phase cleaning have lower interface trap densities than oxides grown after an RCA-based clean.