Using a hot-wall rapid thermal system which permits single-wafer processing, thin gate dielectrics consisting of silicon nitride films were fabricated by low pressure chemical vapor deposition (LPCVD). Nitride layers deposited from dichlorosilane (DCS) and ammonia exhibited greatly reduced electrical leakage current compared to silane-based nitride films which are conventionally used in lamp-based single-wafer rapid thermal technology. After a postdeposition anneal, the DCS-based gate dielectric films showed better diffusion barrier properties against boron penetration than silane-based gate dielectrics at a dopant activation temperature of 1000°C.

There are factors present in cleanroom air that may lead to contamination prior to processing. These factors need to be better understood in order to meet tomorrow's requirement for atomically clean surfaces prior to gate oxidation. This paper identifies the conditions that initiate room temperature oxidation of fluoride prepared hydrogen passivated silicon surfaces by using X-ray Photoelectron Spectroscopy (XPS). Possible oxidation factors investigated include lighting conditions and ambient gases. Both Hx-Si(100) and H-Si(111)(1X1) surfaces do not oxidize in dark conditions and in 450nm wavelength lighting conditions for both humid and dry air ambients. These surfaces do oxidize in dry air and humid air when the surface is exposed to shorter wavelengths of light. Wavelength dependence for oxidation on both surfaces is confirmed. In addition, the level of oxidation observed depends on the surface orientation in humid air but not in dry air.

Thickness uniformities of poly-crystalline silicon thin films, deposited by a commercial LPCVD reactor, were investigated through a phenomenological and elementary reaction analysis. To understand the deposition rate and its profile in radius direction of ø 6”h silicon wafer, concentration distributions of film precursors were examined by solving basic diffusion equations of film precursors in the CVD system. The experimental thickness distribution can be simulated very well with the solution by optimizing η, the sticking probabilities of the precursors. While most of the silicon deposition was made by source precursor (mono-silane, SiH4), two kinds of intermediate species with sticking probabilities of 5X10-2 and 7X10-4 were found to contribute the deposition. Subsequently, elementary chemical reaction analysis of poly-crystalline silicon CVD process was performed using ChemKinTM and two chemical species, SiH2 and Si2H6, were identified as the possible candidates for the intermediate species.

It is accepted that surface Ge atoms are considered to be responsible for the surface B segregation process. A set of original experiments is carried out. A main observation from the B and Ge profiles grown at different conditions shows that at certain conditions B is taking initiative and determine the Ge surface segregation process. basic assumptions are suggested to self-consistently explain these original experimental features and what is observed in the literature. These results have a strong implication for modeling the B diffusion in Si1-xGex where the initial conditions should be formulated accounting for the correlation in B and Ge distribution. A new assumption for the initial condition to be “all B atoms are captured by Ge ” is regarded as a right one implicating that there is no any transient diffusion representing the B capturing kinetics.

Thermal stability of NiSi is a major concern for its application in sub-0.1 μm CMOS devices, due to the transition of NiSi to the high-resistivity disilicide (NiSi2) at elevated temperatures. In this study, we have investigated the effect of RTA silicidation duration on NiSito-NiSi2 transition during Ni-silicidation reaction of Ni film (20-25 nm thick) on (100)Si. It was found that the NiSi-NiSi2 transition temperature was increased remarkably from 700 to > 800 °C by reducing the RTA time from 60 to 1 s. Agglomeration of silicides films was also found to besuppressed by short-time annealing. A temperature-time transformation (TTT) diagram has been constructed, which demonstrates the time-dependency of NiSi-NiSi2 transition. Based on the classical theory on phase transformation kinetics, a concept of induction time was employed to elucidate the key roles of transformation time and film thickness in determining the NiSi-NiSi2 transition temperature.

Constant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Ta films were grown by plasma-enhanced atomic layer deposition (PE-ALD) at temperatures from room temperature up to 300 °C using TaCl5 as source gas and RF plasma-produced atomic H as the reducing agent. Post-deposition ex situ chemical analyses showed that the main impurity is oxygen, incorporated during the air exposure prior to analysis with typically low Cl concentration below 1 at %. The X-ray diffraction indicates that ALD Ta films are amorphous or composed of nano-grains. The typical resistivity of ALD Ta films was 150-180 μΩ cm, which corresponds to that of β-Ta phase, at a wide range of growth parameters. The conformality of the film is 100 % up to an aspect ratio of 15:1 and 40 % for aspect ratio of 40:1. The thickness per cycle, corresponding to the growth rate, was measured by Rutherford back scattering as a function of various key growth parameters, including TaCl5 and H exposure time and growth temperature. The maximum thickness per cycle values were below 0.1 ML, probably due to the steric hindrance for TaCl5 adsorption. Bilayer structures consisting of Cu films deposited by sputtering and ALD Ta films with various thicknesses were prepared and the diffusion barrier properties of ALD Ta films were investigated by various analysis techniques consisting of X-ray diffraction, elastic light scattering, and resistance analysis. The results were compared with Ta thin films deposited by sputtering with comparable thicknesses. Also, the growth of TaN films by PE-ALD using consecutive exposures of atomic H and activated N2 is presented.

A ULK material based on a siloxane resin has been developed that can be processed using spin-coating and thermal cure to yield porous low-k films. The chemical bonds between the resin and porogen groups prevent the phase separation of the porogen from the resin during curing and lead to extremely small pores. The highly hydrophobic thin films made from this material displayed dielectric constant of 1.8, breakdown voltage of 4 MV/cm, a cohesive strength > 60 MPa, excellent crack resistance, and an average pore size of 2.2 nm by Positron Annihilation Lifetime Spectroscopy (PALS) and 2.5-3.0 nm by Ellipsometric Porosimetry (EP). In this paper, our strategy for designing low-k materials, the material properties and initial integration results for this new material will be discussed.

Selective SiGe source/drain technology based on selective deposition of in-situ doped SiGe alloys in recessed source/drain regions can provide junctions with low sheet and contact resistance as well as abrupt doping profiles. This paper examines properties of Ni, Pt and Zr germanosilicides on heavily boron doped SiGe junctions. Our results show that all three metals can form low resistivity germanosilicides on heavily boron doped SiGe alloys. The stability of Ni germanosilicide was found to be limited to about 400°C on undoped SiGe. On heavily boron doped SiGe thermal stability was found to be significantly better possibly due to boron strain compensation. Our findings indicate that on undoped SiGe, thermal stability of Ni germanosilicide could be much enhanced by using a thin Pt interlayer. According to X-ray diffraction analysis, with increasing formation temperature, both Ni and Pt germanosilicides moved toward Ni and Pt monosilicides with signs of excess Ge appearing outside the contact. Analysis of the Pt germanosilicide layers is suggestive of a Ge rich SiGe layer under the germanosilicide. Boron diffusion into Pt and Ni germanosilicides was not observed. On the other hand, a distinct boron peak was observed in Zr germanosilicide suggestive of a stable Zr-B compound. Ultra-shallow junctions with excellent reverse bias behavior were formed using both Ni and Zr germanosilicides.

Non-Fickian effects are accounted for in dopant diffusion by the solution of hyperbolic mass wave propagative equation. The surface flux is represented by a modified Bessels composite function of first kind of 0th order in the open interval of τ>x.

A self-aligned surface MgO layer was used as a mask for dry etching the Cu(Mg) alloy films using an O2 plasma and H(hfac) chemistry. The surface MgO layer was formed by diffusion of Mg from Cu film to the free surface. Cu(4.5at%Mg) film having thickness of 300nm was annealed in O2 ambient at 10 mTorr, 500°C for 30min, followed by the patterning of the MgO layer using photolithography and HF wet etch process. The patterned MgO layer successfully served as a hard mask for dry etching the Cu(Mg) alloy films with a taper slope. In addition, the high quality self-aligned MgO layer was formed upon annealing the Cu(4.5 at.% Mg) alloy films at the low temperature of 300°C. Furthermore, the surface MgO layer grown on Cu(2.3at.% Mg) alloy films at 500°C withstood as a hard mask for dry etching, and thus achieving the patterned copper alloy lines with the low resistivity of 2.2 μΩ-cm. Consequently, this novel etch process using a self-aligned MgO mask can be used for patterning the low resistivity copper alloy lines with a low thermal budget, which is suitable for large-size TFT-LCDs.

The investigation of an alternate approach to nondestructive, nanoscale mechanical imaging for IC interconnect structures is reported. This approach utilizes a heterodyne interferometer based on a scanning probe microscope, also referred to as heterodyne force microscopy (HFM). This interferometer is sensitive to the relative phase difference of the two ultrasonic excitations due to spatial variations in the sample viscoelastic response and enables near-field, phase-sensitive imaging. Proof-of-feasibility demonstrations of this technique are presented for ultrasonic phase-imaging of Al/low-k interconnect structures. Spatial resolution <10 nm is demonstrated.

A general model for charge pumping is derived and is used for extracting interface trap densities using small gate voltage pulses. In MOS structures with ultrathin oxides, this strongly reduces the leakage current and prevents the oxide from any degradation. Interface trap densities from devices with oxides from 2.3 to 1.3 nm thick are reported for the first time.

A low-permittivity (low-k) polymeric material has been synthesized using methyltriethoxysilane as base material. The films were reproduceably deposited, by spin-coating on Si wafers with a uniform thickness in the range of 0.3-0.5μm depending on speed. The parameters for spin coating (spin speed and spin time etc.,) have been optimized. The effects of various curing conditions on the structural and dielectric properties have been studied. Fourier Transform Infrared Spectroscopy (FTIR) shows prominent peaks of Si-CH3 stretch and Si-O stretch modes. Test structures on silicon were fabricated to measure the dielectric constant (k) of the material. The values of k were found to be in the range of 2.6-1.2 for annealing temperatures 150°C-450°C. The dielectric constant decreases as the curing temperature increases.

The work function of a metal gate electrode has been adjusted with the introduction of nitrogen by solid-source diffusion from an over-stoichiometric TiN1+x layer. RBS measurements have shown that measurable concentrations of nitrogen can be diffused into a 10nm Ta layer at moderate anneal temperatures (>500°C), and that this concentration increases with temperature in the range 500-1000°C. Capacitance-voltage measurements have been carried out on 10nm tantalum layers on Al2O3. These measurements have indicated that the work function of tantalum changes by -0.08eV due to the presence of the over-stoichiometric TiN1+x covering layer during anneal (800°C/30”). Similar C-V measurements have been carried out on 10nm molybdenum layers on SiO2 and on Al2O3 dielectrics. These have shown that the work function of molybdenum is substantially different for metal stacks with the TiN1+x covering layer after a similar anneal. The work function changes by -0.52eV for molybdenum on SiO2 and by -1.1eV for molybdenum on Al2O3. The results suggest great potential for molybdenum as a candidate for a single-metal dual-work function approach to integrating metal gates into future CMOS technologies.

Spin-on pre metal dielectric (PMD) materials are being developed for memory and logic devices at 0.10 um design rules and beyond. The stringent design rules require a PMD material with a low thermal budget, excellent gap fill capability, and etch resistance similar to that of a thermal oxide. Spin-on PMD is being developed to meet these requirements as current PMD technologies of HDP CVD and BPSG reflow are constrained by void formation or high thermal budget requirement. One common challenge that faces spin-on PMD is inhomogeneous densification, or “corner etch”. In this paper EELS-STEM, FTIR, SEM and HF wet etching were used to study the mechanism of this phenomenon. This information provides a possible route for the development of spin-on PMD resins.

The capabilities of nanoindentation to characterize low-k organo silicate glass (OSG) thin films is explored as a relatively rapid and inexpensive metric of mechanical properties, adhesion strength, and fracture toughness. One method of decreasing the static dielectric constant of OSG interlayer dielectrics requires the introduction of porosity in the material which has a dramatic impact on its mechanical and toughness properties. Percolation theory is used to formulate a correlation between porosity and elastic modulus. Using cube corner diamond indentation and scratch testing fracture toughness calculations are also discussed.

Aluminum plug technologies are still used for many different semiconductor device applications and are cost-effective processes. However, there are some disadvantages associated with them. The key disadvantage is aluminum junction spiking caused by aluminum diffusing down into the silicon substrate and silicon diffusing up into the aluminum plug due to a poor titanium nitride (TiN) barrier [1]. The tungsten plug process is primarily used for 0.5mm and smaller technologies. Titanium nitride barrier material plays an important role as an underlayer for tungsten plugs to prevent tungsten hexafluoride (WF6) from attacking the titanium (Ti) film [2]. The role of the TiN barrier is to retard or prevent diffusion of the materials that the TiN layer separates [3]. In this work, the authors investigated the TiN barrier film properties with respect to nitrogen flows at two different power set points and argon gas flows. Different experiments were performed to understand the properties of the TiN film with respect to process variables. Single-step and dual-step TiN barrier processes were studied for contact and via step coverage profiles used for aluminum and tungsten plug technologies.

It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.

Experimental results are presented on the diffusion of Cu in silicon and Black Diamond¶ (BD). Cu coated silicon samples, with and without the BD layer, are annealed at various temperatures and times. It is concluded that Cu diffusion in silicon is inhibited in the presence of a copper silicide formed during annealing and/or low solubility at temperatures less than 400°C. On the other hand, the incorporation of Cu in the BD film is observed to be strongly dependant on the method of deposition of the Cu layer. It is further concluded, based on device reliability data, that intentional backside Cu contamination does not pose serious device reliability problems even when subjected to annealing at temperatures typically used for backend processing.