This study investigates and compares the deposition of Hf1-xSixO2 films from two suites of metalorganic CVD precursors. The first precursor suite has oxygen coordinated to the Si or Hf center and includes β-diketonate, alcoxide and acetoxy ligands. The second precursor suite has alkylamido ligands, which have nitrogen coordinated to the Hf or Si center. The process space for deposition of silicates was evaluated for controlling the composition of the silicate films while optimizing deposition rates for a manufacturable single-wafer process. The composition of the film, x, is controlled over the entire range by changing the composition of the precursor solution, Si:Si+Hf. The composition of the films, including hafnium, silicon, oxygen, carbon, and nitrogen content were measured by XPS. Both suites of precursors provide routes by which composition can be controlled in fully oxidized films with low carbon and nitrogen content. Film deposition rates are consistent with manufacturing requirements. The interfacial layers that were observed by HRTEM between the film and the substrate were thin (< 10Å) and possibly graded in composition.

New and emerging process technologies such as Damascene interconnect, metal gate and metal silicide processes are creating metal contamination control challenges for current and future generations of integrated circuits. In this work, we studied the contamination of oxidized silicon wafers by several metals of industrial importance including copper, cobalt, sodium, iron and nickel. Contamination was applied by spin-coating in a range from 20ppb to 500 ppb. Such levels are representative of exposure challenges induced during chemical processes such as CMP (chemical mechanical planarization) cleans. Solvated contamination ions were driven into the oxide layer by corona temperature stress (CTS). The concentrations of metallic species incorporated within the oxide by CTS were quantified using VPD-ICPMS (vapor phase decomposition) and SIMS (secondary ion mass spectrometry) surface analysis techniques. Noncontact COCOS (Corona Oxide Characterization of Semiconductor) methods were employed to measure the electrical properties and reliability of nascent and contaminated oxide/silicon structures. We show that in the absence of significant signals from the surface analysis techniques the COCOS methods show signatures of the metallic contamination in the measurement results.

This paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.

We investigated the evolution of the physical and electrical properties of HfO2 thin films deposited by the reactive DC magnetron sputtering method on the (100) silicon substrate upon annealing. The HfO2 thin films deposited at room temperature were amorphous, while the films after annealing were poly crystalline. The crystallization temperature of the HfO2 thin films was dependent on the annealing methods (RTP or Furnace) and ambient (nitrogen or oxygen). The microstructures of HfO2 thin gate oxides of Tox <15A thick were analyzed by HRTEM, XPS and XRD. We also focused on the interfacial layer between HfO2 thin films and silicon substrates. Due to its high oxygen diffusivity, any annealing led to oxygen diffusion rapidly through the HfO2 films. The EOT increased upon annealing due to the increased SiO2-containing layer. The HfO2 thin films deposited at room temperature have the undesirable interfacial states due to the surface damage by sputtering. We found that the HfO2 thin films <15A thick were optimized by RTP or furnace annealing.

High purity Ni films from 200Å down to 40Å on p-type Si (100) substrates are treated by rapid thermal annealing to form the metastable and stable phases of nickel silicides. The stoichiometric composition of NiSi determined by Rutherford backscattering is independent of the initial Ni thickness under 500°C annealing. Channeling RBS results reveal that the NiSi growth on Si (100) has no preferred orientation. The sheet resistance as well as surface roughness of thinner films starts to increase at a lower temperature, indicating that thinner films are thermally less stable. Agglomeration of NiSi film agrees with the grain boundary grooving model and occurs more easily within thinner films. The transformation from the NiSi phase to the NiSi2 phase is studied by micro-Raman spectroscopy. This phase transition of thinner films begins at a lower temperature than that of thicker ones.

We describe the preparation, properties and the comparison of SiO2 films deposited by liquid phase deposition from supersaturated solutions with both silica powder and silicic acid. From each solution the resulting [Si (OH)4]-rich supersaturated solution, when suitably diluted with De-Ionised (DI) water deposits SiO2 onto silicon. Our work was motivated by the search for the optimum condition for device quality oxide growth within a low (<300°C) thermal budget, for large area device fabrication, on inexpensive substrates such as glass and plastic. The net growth of the LPD of the oxide layer is result of competition between deposition and etching; the balance and hence the rate of growth being controlled simply and reproducibly by the addition of de-ionised (DI) water. We have produced device grade SiO2 from the solution at 48°C onto both n and p type Si substrates. Control of the oxide properties is achieved in the amount of DI water added to the super-saturated solution. Oxide layers of optimum quality being obtained by the titration of 60ml DI water to 100ml of supersaturated solution. FTIR, ellipsometery, and C-V/I-V measurements were used to characterise the films deposited from solutions of silica powder and silicic acid. The resistivity of the optimum layers from a saturated solution of silica powder was found to be of the order of ≈1011 Ωcm with breakdown field strengths of the order of 3-5 x 106 V/cm. The resistivity of the optimum layers prepared using silicic acid were much higher (1015 Ω-cm), with breakdown field strengths of the order of (9±1) x 106 V/cm. The results approach those for thermally grown silicon dioxide, suggesting that LPD oxide have the potential of device quality insulator on large area substrate.

Particles emanating from the walls, shields, and other components of the chambers in which integrated circuit wafers are processed, are among the factors which have been shown to contribute to the formation of defect sites on the completed wafers. Typically, the generation rate of these particles is influenced by the final treatment that the surfaces of these components receive prior to installation in the chamber, whether or not the components are new or recycled. Parameters affecting one such source of particulate contamination have been examined in the present studies.

In this paper we discuss a new method for measuring border trap density (Nbt ) in sub-micron transistors using the hysteresis in drain current. We have used this method to measure Nbt in jet Vapour Deposited (JVD) Silcon Nitride transistors (MNSFETs). We have extended this method to measure the energy and spatial distribution of border traps in these devices. The transient drain current varies linearly with logarthmic time. This suggests that tunneling is the dominant charge exchange mechanism of border traps. The pre-stress energy distribution is uniform whereas poststress energy distribution shows a peak near the midgap.

The effect of microstructure of dc magnetron sputtered TiN and TaN diffusion barriers on the palladium activation for autocatalytic electroless copper deposition has been investigated by using X-ray diffraction, sheet resistance measurement, field emission scanning electron microscopy (FE-SEM) and plan view transmission electron microscopy (TEM). The density of palladium nuclei on TaN diffusion barrier increases as the grain size of TaN films decreases, which was caused by increasing nitrogen content in TaN films. Plan view TEM results of TiN and TaN diffusiton barriers showed that palladium nuclei formed mainly on the grain boundaries of the diffusion barriers.

This work deals with the analysis of the resistances of Co-silicided As and B junctions. The influence of junction formation and salicide process on contact resistance was investigated. The contact resistance between the silicide and source/drain region was studied by making use of dedicated transmission line structures. The transmission line structures (TLM) consist of alternating silicided and unsilicided diffusion segments, obtained by making use of a salicide blocking mask. Our TLM results show that the contact resistance has a strong dependence on the doping profile of the diffused region and increases with decreasing surface doping, with increasing Co-silicide thickness, annealing temperatures and time of silicidation.

The advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

The success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.

A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

The paper presents the results of study of carbothermic reduction method for solar grade silicon (SG-Si) production. The interconnection between the purity of source materials and derivable silicon has been established. The technological concept of SG-Si production, including source materials preparation, carbothermic process, silicon filtration and crystallization is suggested. The comparative analysis data of different methods of SG-Si is given.

Mg- doped Ba0.96 Ca0.04 Ti0.84 Zr0.16 O3 (BCTZ) thin films were fabricated on Pt/MgO substrate by metallorganic decomposition method. The structures of the films were analyzed by x-ray diffraction. The electrical measurements were performed on metal-ferroelectric-metal capacitors with platinum as the top and bottom electrode. The dielectric properties were improved after the capacitors were post annealed at 700 °C in oxygen atmosphere for 30 min. A high dielectric constant of 504 and a dissipation factor of less than 4% was obtained at 1 MHz. The Pt/BCTZ/Pt/MgO capacitors exhibited high tunability of 55% at an applied field of 55 kV/cm.

Oxide/Nitride dielectric stack is widely used as the standard dielectric for DRAM capacitors. The influence of the chemical cleaning prior to the stack formation has been studied in this work. As a result, morphological data such as stack surface roughness (Atomic Force Microscopy) and silicon nitride (SiN) incubation time for growth are comparable for all the studied cases on <Si>. However, Tof-SIMS exhibits different oxygen content at the Si/stack interface following the different chemical treatments. Electrical measurements show comparable C-V and I-V results, for the same Equivalent Oxide Thickness (same capacitance at strong accumulation i.e.-3V) while the different studied interfaces bring different interface states density with lower values for higher interfacial oxygen content. For DRAM applications, a clear improvement in electrical characteristics is obtained under low interfacial oxygen content conditions. Results are compared in embedded-DRAM cells for which we developed an industrially compatible dielectric deposition sequence to obtain minimum leakage current with maximum specific capacitance and no particular linking constraints.

We propose and demonstrate experimentally a structural characterization technique for ultra-low-dielectric-constant thin films with periodic porous structures [1-3] by employing X-ray diffraction / scattering measurements. The analytical approach that we propose here takes into account specular reflection, incoherent scattering from random distribution of electron density, and coherent scattering from periodically modulated distribution of electron density. From the analysis, inter-pore distances and pore diameters in the directions perpendicular and parallel to the film surface are determined with which the film porosity is calculated. Thus obtained porosity is then used to discuss the film density and dielectric constant in comparison to those of non-porous reference sample.

A metal-organic atomic layer deposition (ALD) tantalum nitride process has been demonstrated for zero-thickness liner applications in advanced copper metallization schemes. Utilizing a commercially available ALD reactor, this process employs a liquid tantalum source (tertbutylimido tris(diethylamido) tantalum—TBTDET) and ammonia as the reactants. Key functionality data addressing the self-limiting nature of ALD film growth with respect to key process parameters including processing temperature and the substrate surface exposures to TBTDET and ammonia have been obtained, leading to the establishment of an optimized ALD processing window. Highly conformal, continuous, and smooth growth over high aspect ratio structures is exhibited, and incubation periods appear to be relatively substrate independent. Preliminary thermal and electrical copper barrier performance testing of the deposited films indicates that they hold promise for use in emerging nanoscale interconnect applications.

The thermal stability of organic porous low k, porous SiLK with a dielectric constant of 2.4, has been studied. Organic low k material SiLKTM, non-porous SiLK, with a dielectric constant 2.8 is used as a baseline for comparison. Each sample was subjected to annealing cycles, where each cycle was conducted in a vertical furnace for one hour in an N2 ambient. The annealing temperature was set at either 430°C or 450°C. After every alternate cycle, the film properties were measured and compared to the unannealed sample for changes in film shrinkage, refractive index, dielectric constant, roughness, breakdown voltage, pore size, hardness and Young's modulus. Changes in film properties were investigated and evaluated by using opti-probe, FTIR, XPS, AFM, mercury probe, nano-indentation, SEM and TEM techniques.

High purity silicon amido precursors provide a route to low temperature CVD of silicate gate dielectrics. We have developed a straightforward synthetic method for the production of high purity Si[N(CH3)2]4, Si(NMeEt)4, HSi(NEtMe)3 and HSi(NEt2)3 in high yield. These compounds were fully characterized by NMR, GC/MS, ICP-MS, ICchlorine, and elemental analysis. Their solution compatibility with an Hf amide source was also examined by chemical techniques. Low temperature CVD of metal silicate films is also demonstrated.

A mesoporous silica film was prepared on a silicon substrate using a spin-coating process followed by a tetraethyl orthosilicate (TEOS) vapor treatment. The stability of a formed silica network before TEOS treatment is thought to be insufficient because the rate of the condensation reaction is not high at temperatures below 453 K. The density of silica wall surrounding surfactant assembly could be low, resulting in the structural contraction with the formation of a silica network. On the other hand, the TEOS-treated mesoporous silica film did not contract during calcination, showing high structural stability. In the TEOS treatment, TEOS molecules penetrate into an originally deposited silicate film and react with silanol groups. The densified silica wall has high structural stability and hardly contracts under a calcination process. A flat mesoporous silica film about 250 nm thick was grown from the silicon substrate. A periodic hexagonal porous structure was observed in the FE-SEM image of the cross section of the TEOS-treated film. This indicates that the channels run predominantly parallel to the surface of the silicon substrate. The developed film is a promising material such as chemical sensors, low-k films and other optoelectronic devices.