High tensile stresses develop in passivated aluminum line metallizations on silicon substrates after excursion to elevated temperatures. The principal mechanisms to relax these stresses at room temperature are plastic deformation and grain boundary void growth. It is shown that stress relaxation and void growth are intimately connected.

Stress relaxation was studied in bare and nitride-covered continuous films and narrow lines of aluminum. The rate of relaxation in unpassivated metallizations is shown to be consistent with a dislocation-controlled mechanism. Relaxation in passivated lines appears to depend on grain boundary diffusion-controlled void growth. In passivated continuous films, two rate-controlling mechanisms appear to operate in sequence.

It is well known that the grain size of interconnections made from aluminum alloys affects electromigration and stressmigration tolerance. The hardness of three kinds of aluminum alloys is measured and it is shown that it has a strong correlation between the grain size of the aluminum alloy films. Stressmigration testing is done for those aluminum alloy films and it is found that the SM tolerance of aluminum films can be judged by the hardness of the films. Electromigration testing is also done and the results also confirm the correlation between EM tolerance and hardness of the aluminum films. Hardness measurements are simple and have the possibility of rough estimation of EM and SM tolerance. This method have the merit of saving time for life test.

We have developed a numerical model for calculating stresses generated during cure of shrinking encapsulating resins. Mechanical modeling of polymer encapsulated electronic devices usually focusses on stress generated during cooling after cure. The stress developed during cure, due to shrinkage of the encapsulant, is normally neglected. That assumption is valid if both the shear and bulk moduli of the encapsulant at the cure temperature are negligible with respect to the moduli at lower temperatures. Our measurements on a model epoxy encapsulant show that the shear modulus during cure, varying from 0 to 6 MPa, is at least 100 times smaller than that at ambient temperature. In contrast, the bulk modulus at the cure temperature is only 2.5 times smaller. Since the bulk modulus during cure cannot be neglected, significant stress can be produced if volume shrinkage is constrained by a stiff mold or embedded elements. In fact, mechanical failure of encapsulating materials during cure has been evident in some of our experiments. Using measurements of shear and bulk moduli plus volume shrinkage as inputs to a finite element model, we have successfully predicted the shrinkage strains and stresses developed during cure of a model epoxy resin inside a cylindrical tube. Consideration of cure shrinkage stress has led to a process modification that appears to reduce mechanical failures in a real encapsulated device.

Silicon carbide whisker reinforced aluminum with improved temperature resistance, increased tensile strength and decreased coefficient of thermal expansion was obtained by using a phosphate binder instead of a commonly used silica binder for preparing the SiC whisker preform, to which liquid aluminum was infiltrated in order to form the composite. The composite is attractive for applications as a heat sink with a low coefficient of thermal expansion.

Even at room temperature, solder joints exhibit both creep and fatigue behavior that is strongly dependent on solder joint configuration, the thermal environment, and the solder alloy properties. The microstructures of solder joints with up to 25 years of aging have been studied using SEM/EDS and metallographic techniques. Data are presented on grain growth and metallurgical composition versus aging time. A special non-linear finite element creep-fatigue simulation model has been developed, based on measured strain-rate hardness relationships, and used to analytically predict the effects of observed metallurgical changes and the effects of lead stiffness in solder joint creepfatigue interaction. To corroborate the analytical results, a special bi-metallic test fixture has been developed to accelerate the thermo-mechanical loading of solder joints in thermal cycling environments. Measured time-to-failure data for various electronicpackage lead configurations/stiffnesses, including gullwing and J-lead, are presented and shown to be in reasonable agreement with the analytical results.

In this paper, a numerical simulation of thermal process in the SMT laser microsoldering joint has been developed, in which, the influence on thermal process of the factors such as the thermal conductivity variation of solder with temperature, light reflection coefficient of the lead wire surface, and heat exchange on the surface of SMT materials all have been considered. In order to carry this numerical calculation practice and prove it's results, the reflexive characteristic of light wave to the SMT materials has been gauged, and the dynamic temperature process of laser microjoint has been measured by a new experimental method which was invented by the authors.

The results of numerical simulation have been borne out by the tests, and the influences of heating parameters on thermal process has been analysed in this paper. The conclusions will be advantageous to the further study of the microjoint quality control in the SMT laser microsoldering.

In this paper, the forming process of copper wire ball in copper ball bonding has been studied by numerical analysis. By means of calculation of temperature field, speed field and displacement field for ultrafine copper wire under a miniarc, the regular pattern of copper wire ball formation has been clarified. In this paper, the calculating result of displacement field has also been tested and verified.

The reliability of silicon integrated circuits (ICs) has improved significantly in the last decade. The complexity of ICs continues to increase. The semiconductor industry is actively working to a) improve the reliability of very large scale (VLSI) ICs, and b) reduce the failure rates to a value closer to 0.1 FIT by the year 2000. This paper summarizes the current status of quality and reliability of ICs. Some of the reliability limiting factors are described. Inadequacy of conventional accelerated test methods to verify the reliability of VLSI devices is highlighted. A challenging VLSI reliability goal with a failure rate approaching 0.1 FIT requires a) an understanding of the root causes of failure mechanisms, b) a translation of the lessons learned into a set of design rules for the circuit designers, c) appropriate materials and process specifications consistent with manufacturing capabilities, and d) in-process reliability test structures and test procedures. A VLSI failure rate goal of 0.1 FIT presents an exciting challenge for the materials scientists.

Microstructural evolution in thin-film strips is of interest due to the direct effect of grain structure on integrated circuit interconnect reliability and resistance to electromigration-induced failure. We have explored the evolution of interconnect grain structure via a two-dimensional grain growth simulation. We focus on the strip's transformation to the bamboo structure, in which individual grains traverse the width of the strip. We find that the approach to a fully bamboo structure is exponential, and that the rate of transformation is inversely proportional to the square of the strip width. When the simulation is extended to model grain boundary pinning due to grooving at grain boundary – free surface intersections, we find that there exists a maximum strip width to thickness ratio beyond which the transformation to the bamboo structure does not proceed to completion. By using our simulation results in conjunction with a “failure unit” model for electromigration-induced failure [4] we are able to reproduce the experimentally observed abrupt increase in time-to-failure below a critical strip width, and also model the reliability as a function of annealing conditions.

Backscattered electron imaging of microcircuits in scanning transmission electron microscopes at 120 kV is shown to produce improved images of voids in passivated Al metallization lines relative to those obtained with scanning electron microscopes at ≤ 40 kV. At 120 kV, resolutions of about 0.1 μm are achieved for voids imaged beneath 1.0 μm glass overlayers. This technique allows improved characterization of microstructures for basic investigations of void formation and more accurate counting of voids in microcircuits without removing glass overlayers. Smaller voids should also be detectable with the higher voltage.

The reliability of copper multilevel interconnections requires good adhesion and the prevention of copper diffusion into the interlevel dielectric. Magnesium is a candidate for an adhesion layer and diffusion barrier for copper due to the high heats of formation of magnesium oxides, fluorides and sulfides and the formation of low resistivity compounds of Mg with copper. An investigation of the interactions in thin films of copper and magnesium has been carried out in the temperature range of 25°C to 500°C. The results of these reactions leading to phase formation in Cu/Mg bilayers deposited on Si3N4 or SiO2 using X-ray diffraction, in situ sheet resistance, and Rutherford backscattering measurements are presented in this paper. It was found that the Mg-rich phase CuMg2 is the first phase to form on annealing to approximately 215°C, followed by the formation of the Cu-rich phase Cu2Mg at about 380°C in the presence of excess Cu.

Tantallum silicide films were sputter deposited from targets with different Si/Ta stoichiometries. The films were then subjected to thermal treatments. Silicon precipitation was observed on films deposited from silicon rich targets. The effects of silicon precipitates on device characteristics was studied. A method to suppress silicon precipitation is reported.

The influence of the localized defective channel region formed by hot carrier injection on the basic characteristics of P-channel transistors is systematically investigated and modeled. A practical method of parameter extraction in stressed P-MOSFET's is proposed. It is based on the comparison of Ids(Vg) characteristics before and after stress in weak and strong inversion.

The effects of post-gate processing in N2+O2 (0˜40%) ambient (e.g., source/drain annealing, BPSG densification and reflow) on the initial MOS characteristics and reliability are discussed in this study. In comparison with processing in pure N2 ambient, it is found that processing in N2+O2-enriched ambient causes a significant, but, transient low-field breakdown of MOS capacitors on both n- and p-wells when electron injection occurs at the poly-gate/SiO2 interface. As a result, the p-channel MOSFETs with high concentration-O2 (˜40%) processing have an excess (i.e., two orders of magnitude) gate leakage current. The experimental results seem to suggest that the annealing in O2-enriched ambient (vs. pure N2 ambient) may induce positive charges near the poly-gate/SiO2 interface which reduce the electron tunneling barrier. Our results also suggest that the induced positive-charges are annihilated immediately upon the application of electric fields.

There has been some uncertainty as to the impact of fluorine (F) on SiO2 quality and reliability. Several laboratories have shown greatly enhanced quality and reliability with fluorinated oxides, while others have been unable to repeat the results. In addition, the laboratories which have shown enhanced reliability with the fluorinated oxides have differed in their interpretation of the mechanism by which the enhancement occurs. X-ray diffraction stress measurements, partial time dependent dielectric breakdown (TDDB) measurements, SIMS depth profiling, transmission electron microscopy, standard high/low frequency C-V measurements, and hot-carrier aging of variously processed MOSFETs have been used to investigate a variety of fluorinated films. We believe that the apparent lack of consistency of the effects of fluorine on MOSFET reliability between laboratories may be explained by slight variations in the gate polysilicon processing which result in variations in polysilicon morphology. The polysilicon morphology determines both mechanical stress and F diffusion which ultimately impacts interface state density and thus hot carrier reliability.

Recombination lifetime of a epitaxial layer (epilayer) is automatically measured by using the conductivity modulation technique. A lateral p+-n−-n+ diode test structure on the surface of the epilayer is formed to evaluate the minority carrier lifetime. Depth profiles of the recombination lifetime are obtained from current-voltage curves of a lateral p+-n−-n+ diode and a vertical n+-n−-n+ structure between the substrate and the top surface. We measure the lifetime in epilayers with and without a buffer-layer. In addition, photo-response of photodiodes with and without the buffer-layer is measured. Profiles of the recombination lifetime depend on the thickness of the epilayer but not on the thickness of the buffer-layer. Minority carrier lifetime in the epilayer, and the leakage current and the photo-response of photodiodes are improved by the buffer-layer formation between epilayer and substrate.

Determination of the failure mechanisms and failure rate of oxide wearout by hot carrier injection in submicron metal-oxide-semiconductor field-effect-transistor (MOSFET) requires special test structures to isolate the oxide field dependence of oxide trap generation and charging. A bipolar-MOS transistor (BiMOS) structure is used which d.c. injects substrate electrons into the gate oxide of a MOS transistor by forward biasing the emitter-base n+/p junction of a vertical n+/p/n-inversion-layer bipolar junction transistor. The field and temperature dependences enable a separation of thermal and tunnel electron detrapping rates at low and high oxide field from the generation rate of new oxide traps at high fields. Pulsed a.c. substrate electron injection in a n+ sourced metal-oxide-semiconductor capacitor (SMOSC) structure is used to characterize the field dependence of oxide degradation in chlorinated oxides.

Silicon dioxide (SiO2) films were fabricated by microwave ECR plasma processing at 300°C, the range of the film thicknesses being 200 - 300 Å. Two groups of films were fabricated; group A with the substrates placed in a position directly facing the plasma so that the substrates as well as the on-growing films were subjected to bombardment of energetic particles produced in the plasma, and group B with the substrates placed in a processing chamber physically separated from the plasma chamber in order to prevent or suppress the damaging effects resulting from these energetic particle bombardment. It has been found that group A films are poor in both the capacitance-voltage (C-V) and the current-voltage (I-V) characteristics, possibly due to dust particles created by the gas phase reaction of SiH4 and ionic bombardment and radiation damage during film deposition. Group B films, on the other hands, exhibit good electronic properties. On the basis of their I-V and C-V characteristics, group B films yield an average breakdown strength of about 10 MV/cm, an oxide bulk charge density on the order of 1014 q/cm3 and an interface trap density on the order of 1011 cm−2 eV−1 which are approaching those of high quality thermally grown oxides and they are suitable for use as gate insulator for MOS devices.

This paper presents a TEM investigation of undoped, semi-insulating GaAs crystals grown by the VGF (vertical gradient freeze) technique for microstructure and defects characterization. Energy dispersive X-ray spectrometry (EDS) and selected area electron diffraction (SAD) were used to characterize for composition and lattice spacings, respectively. TEM images of dislocations decorated with precipitate particles are presented. The particles were found to be arsenic rich. Regions of fine particulates were identified and a Moire pattern analysis was carried out. The occurrence of such defects in the low dislocation density VGF GaAs of the present study suggests that these are material related and not necessarily dependent on the growth technique.