Electron spin resonance and its use as a tool for building reliability into MOS oxides is reviewed.

We have observed fluctuations in the tunneling current through 3.5 nm gate oxides with a 1/f power spectrum where f is the frequency. For voltages in the direct tunneling regime we lind an anomalous current dependence of the noise relative to previous observations of noise in thin oxides. We present a simplified model for the current noise in terms of fluctuations in a trap assisted tunneling current that exists in the oxide in addition to the direct tunneling current. Current noise appears to be a very sensitive probe of trap assisted tunneling and degradation in oxides.

High field electron injection in silicon oxide layers in metal-oxide-semiconductor system is widely known to degrade thin silicon oxide layers and the silicon-oxide interface, eventually leading to catastrophic oxide breakdown. In this work we report generation of hole traps under high-field stressing of thermal silicon dioxide layers on silicon. Excess hole trapping on newly generated hole traps is observed by substrate hot-hole injection in 9 nm oxide PMOS transistors after high-field Fowler-Nordheim stress followed by standard post-metallization annealing in nitrogen. The concentration of generated traps is stress-polarity dependent and increases with electron fluence during degrading stress. Relaxation behavior under switching oxide fields indicates that the nature of hole trapping sites is different from anomalous positive charge centers. A correlation of density of generated hole traps with the amount of generated electron traps shows that both types of traps are effectively generated in the oxide layer under Fowler-Nordheim tunneling electron injection.

We present the results of experiments studying the effect of carrier depletion and interfacial stress on time to breakdown of'thin oxide films during constant current stressing High energy electrons resulting from carrier depletion conditions increase damage to oxides during tunneling. Carrier depletion conditions cause a dramatic decrease in time to breakdown and increase the number of early failures substantially. Mechanical interfacial stress results in a degradation in oxide reliability. Anode interfacial stress has been uniquely isolated from other phenomena such as cathode surface roughness, and has been shown to result in accelerated breakdown. These results have implications on oxide reliability and on test methodologies to obtain a measure of the same

New insights into the nature of oxide trapped holes and other defects have been gained from ionizing radiation studies. Specifically, connections have been established between hole traps and neutral traps. The nature of the defects, how they are related to each other, and their implications for reliability studies will be discussed.

Stress-induced trap levels near Si/SiO2 interfaces for MOS diodes with 10 imi-thick oxides are investigated by measuring the transient photocurrent, which depends on the incident photon energy. The electron trap levels are filled by tunneling injection, and the electrons are depopulated by monochromatic light irradiation. The transient photocurrent, which is measured as an external circuit current, decays exponentially with time. Based on a proposed detrapping model, the optical cross section is estimated to be about 1×10−17 cm2 for hv=2−3 eV. The obtained photo-accessible trap density has a broad distribution at around hv=2.5 eV.

This paper investigates the sensitivity and limitation of capacitor testing for measuring potential charging damage to gate oxides in a given plasma step. While C-V measurements are the most directly related to transistor threshold voltage (Vth) and transconductance (gm), C-V measurements are slow, difficult to automate and not usable for large antenna structures without a fuse link. In contrast, ramp breakdown measurements are quick and easy to automate but lack sensitivity. Charge-to-breakdown offers better sensitivity but with long measurement times. A more promising method is the V-t measurement where the slope dV/dt after initial charging is a measure of the trapping generation rate and is found to be very sensitive to charge damage. The damage sensitivity of this method is high and involves tradeoffs between antenna ratio, testing current and testing time. All of which are critical to damage testing. Leakage measurements are another method which offers short measurement times and high sensitivity. Their limitations are the noise level of the measurement system and the making of good probe contact to the gate material.

In this work we demonstrate that in MOS devices the reliability of ultrathin (< 100Å) gate oxide is a strong function of growth conditions, such as, temperature and the growth rate. In addition, for constant current gate injection the degradation of SiO2 is enhanced as the thickness is reduced. We attribute this to physical stress in SiO2 resulting from the growth process. The degradation is always more for those growth conditions which result in higher physical stress in SiO2. Higher temperatures and slower oxidation rates allow stress relaxation through viscous flow and hence result in SiO2 of better reliability. We also found that for constant current stressing, the interface damage is more at the collecting electrode than at the injecting electrode. ΔDit (stress induced interface state generation) can be reduced after a high temperature Ar post anneal after the gate oxide growth.

In this paper, the impact of several front-end processing steps (up to gate oxidation) on gate oxide integrity (GOI) is evaluated. In PBL isolation processing, the use of as-deposited amorphous silicon (a-Si), subsequently annealed during nitride deposition, results in better structural and electrical properties compared to as-deposited polysilicon or as-deposited a-Si with an extra anneal step prior to nitride deposition. Thicker or dual sacrificial schemes exhibit improved gate oxide low voltage breakdown and charge-to-breakdown. Dilute RCA chemistries during pre-gate cleaning produce equal or better surfaces for gate oxidation than the conventional non-dilute RCA with less chemical usage. As gate oxides are scaled below 100Å, lowering gate oxidation temperature is proven to result in far better gate oxide quality than maintaining process temperatures at or above 900°C and diluting oxygen in either argon or nitrogen.

Silicon dioxide films were reactively sputter deposited in argon/oxygen ambient using RF magnetron sputter deposition techniques. A substantial drop in the deposition rate at high enough partial pressure of the oxygen which is typical in reactive sputtering was observed. The best quality silicon dioxide films were obtained at the lower deposition rate, close to the deposition rate transition point. Higher quality films were obtained at higher RF powers with higher deposition rates. However, at 800 Watts RF, the so called negative ion effect dominates and results in higher surface roughness of the films, as seen by AFM results. Various characterization techniques including ellipsometry and wet chemical etching were used to compare stoichiometry and film density, respectively. MOS capacitor characterization along with breakdown voltages were also measured as a means of qualifying the films.

The reduction of mobile ions--mainly Na+, but also K+, H+ and Li+, is very critical as our gate oxide thickness and Leff decreases. Hot electron induced hydrogen compensation of boron doped silicon changes the PMOS Leff and NPN BVebo. This paper shows how to reduce Na+ by 100X, through the use of Triangular Voltage Sweep (TVS). This paper is designed to give scientists and engineers a case history where we reduced these levels from 1012 to 1010 mobile ions/cm2 in our 0.8μm BiCMOS process. This was accomplished by adding Ammonium Fluoride mixture dips at appropriate steps. For fast feedback, we can non-destructively measure Na, K, and H within 10 minutes of completing phororesist removal at any of the metallization steps using TVS. In addition to BiCMOS, TVS measure is a power tool in Nonvolatile Memories for predicting in-line data retention, when data retention is associated with charge gain.

This paper presents a systematic investigation of the hot-carrier effect in deep sub-micron silicon nMOSFET devices. A Hydrodynamic model for semiconductors was used to simulate the local carrier heating and the non-local transport phenomena in nMOSFETs of effective channel lengths 41, 66, 96, and 126 nrn under various biasing conditions. Test structures for device simulation were generated by using a super-steep retrograde channel profile with subsurface peak concentration of l×1018 cm−3, and a gate oxide thickness of 3 nm. Superb MOSFET device characteristics were obtained for all devices. The simulation results show a significant decrease in substrate current, electron impact ionization rate, and peak electron temperature near the drain end of the channel with the decrease in supply voltage. The distribution of electrons into the substrate due to local electron heating is shown to be responsible for hot-carrier reliability in ultra-short channel silicon nMOSFET devices.

This paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

A series of investigations have been conducted into the properties of N2O silicon oxynitride gate dielectrics, and the various methods of their growth. One of the principle advantages of these oxides is their resistance to interface state generation. This is linked to the presense of nitrogen near the substrate interface, where it is triply bonded to silicon. It is also demonstrated that during N2O-based furnace growth, the total concentration of NOx species varies strongly with the flow rate of N2O. This has been correlated to the temperature profile of the furnace, which can be affected by the exothermic decomposition of N2O. This property has been exploited to controllably adjust the rate of nitrogen incorporation by up to a factor of three. Although nitrogen incorporation during furnace processing is generally stable, it is shown that atomic oxygen is capable of removing previously incorporated nitrogen. Sources of atomic oxygen include the decomposition of N2O during RTP treatment, N2O processing in a high flow rate furnace, or from ozone annealing.

The electrical characteristics of thin gate dielectrics prepared by low temperature (850 °C) two-step N20 nitridation (LTN) process are presented. The gate oxides were grown by wet oxidation at 800 °C and then annealed in N2O at 850 °C. The oxide with N2O anneal, even for low temperature (850 °C), had nitrogen incorporation at oxide/silicon interface. The charge trapping phenomena and interface-state generation (ΔDitm) induced by constant current stressing were reduced and charge-to-breakdown (Qbd) under constant current stressing was increased. This LTN oxynitride was used as gate dielectric for N-channel MOSFET, whose hot-canrier immunity was shown improved and reverse short channel effect (RSCE) was suppressed.

This work describes a two-step, lightly nitrided gate oxidation process for sub-0.5 jtm CMOS technology. This process is a simple extension of conventional oxidation using an in-situ N2O post oxidation anneal for nitrogen incorporation. Light nitrogen incorporation (∼3%) near the Si/SiO2 interface has improved oxide characteristics such as defect density (Do.), wear-out (Nbd), breakdown (Vbd) and tunneling (VFN) without altering its charge trapping behavior. Impacts of nitridation are more significant for thinner (<65Å) gate oxides (GOX).

Leakage currents through MIS (Metal Insulator Semiconductor) structures with several ultra-thin (14–30Å) insulators (silicon dioxide, silicon oxynitride, and silicon nitride) have been investigated. The leakage currents through both dioxide and oxynitride films sandwiched between n-type poly-Si gates and n-type substrates can be well fitted by the equation for the electron direct tunneling mechanism using the same effective mass and barrier height. This result indicates that incorporation of a minute amount of nitrogen atoms does not seriously affect the basic electrical properties of the oxide films. Leakage currents through ultra-thin nitride can te also fitted with the equation for the direct tunneling mechanism without assuming any extra conduction mechanisms such as hopping through defects.

Siliconoxynitride layers with thicknesses between 5 and 10 nm were grown on (100) oriented silicon by rapid thermal processing (RTP) using either N2O or NH3 as nitridant. In order to study the trapping behaviour at the interface and in the insulator bulk, capacitance-voltage (CV) and current-voltage (IV) measurements have been performed combined with different magnitudes of Fowler-Nordheim stress. In addition, Deep Level Transient Spectroscopy (DLTS) has been applied for interface state detection. Auger Electron Spectroscopy (AES) has been used to obtain depth profiles for Si, N, O and C. The deconvolution of the AES signal displays significant peak contributions related to intermedium oxidation states. Nuclear Reaction Analysis (NRA) was successfully applied for hydrogen detection in buried SiOxNy thin films.

In CMOS, the addition of chlorine particularly in TCA form to the growth of thermal oxides in logic technologies is well-known and pervasive. In addition to the increasing environmental concerns of chlorine use, one of the important parameters is the amount of metallic contamination due to transition metals such as Fe in the Si, and alkali metals like Na in the oxide since these phenomena effect both device performance and quality. However, the ability to measure this parameter on product material is not generally available due to inherent problems with most known methods. In this paper we report on the application of high-injection, frequency based optical surface photovoltage (SPV) and a more recent technique known as a contact potential difference (CPD) to both quantify and qualify as-grown oxides on CZ P-type silicon.

A new generation of monitoring tools based on oxide potential and surface photovoltage measurements offers real-time, non-contact diagnostics of plasma damage, especially dielectric charge build-up, radiation damage, and heavy metal contamination. The approach relies on reusable, 10 00Åoxide monitor wafers rather than test structures. The technique generates whole wafer maps powerful for correlating plasma damage with plasma equipment characteristics.