Volatile organic surface contaminants on silicon wafers lead to strong detrimental impact on semiconductor production yield and product reliability. Our model for the mechanism of impact is introduced and discussed.

Only a few metrology methods are suited for the ultratrace detection of volatiles on surfaces and their identification. The data presented in this paper were achieved by ion mobility spectrometry followed by mass spectrometry (IMS/MS).

Eleven commercial wafer storage and transport boxes were screened by sampling the contaminants onto silicon wafers at room temperature. In a second set of experiments, enhanced stress testing was performed at elevated temperatures for polypropylene, polycarbonate, polytetrafluoro ethylene, perfluoro alkoxy polymer, polyvinylidene fluoride and acrylonitrile-butadiene-styrene copolymer. From the outgassing behaviour of single contaminants, valuable information can be achieved.

Test method E 46 (SEMI) samples the contaminants onto the wafer under the real conditions of use. The data for six virgin minienvironments are shown.

Surface contamination and chemical stability of hydrogen terminated Si(100) surfaces have been studied using Fourier Transform Infrared Attenuated Total Reflection (FT-IR-ATR) spectroscopy and X-ray Photoelectron Spectroscopy (XPS). Hydrogen terminated Si(100) is obtained by removing the chemical oxide, formed in a low-concentration-NH4OH SC1 clean, in various HF based solutions. Using standard cleaning and loading conditions, we find a direct correlation between surface roughness and the amount of adsorbed C contamination. Oxidation during water rinsing and wafer loading observed by both FT-IR-ATR and XPS indicates that dihydride terminated silicon atoms are preferentially oxidized. Optimizing the water rinse and wafer loading conditions reduces total atomic concentration of C, O, and F surface contamination from 20–30 at.% to less than 6 at.%. These clean surfaces enable XPS-identification of the Si-Hx components of the Si 2p core-level spectra as well as estimation of the relative surface concentration of Si-Hx and contamination species.

The outplating behaviour of Fe and Cu was investigated for diluted solutions of HCl and HNO3. The deposition of the metallic contaminants was found to be strongly dependent on the type of surface that is exposed to the contaminated solution. Cu deposits heavily on bare silicon surfaces, whereas only low levels of Fe deposition are observed. On the other hand, on thermal oxide surfaces, the levels of deposited Fe are consistently higher than the Cu ones. The acid used appears to have no major impact on the deposition process. The pH of the solutions has a major effect on the Cu deposition and a minor effect on the Fe case.

There is a need in the semiconductor industry to develop new techniques and instrumentation for the elemental and chemical analysis of submicron, particularly <0.2 μm, particles. The development of these techniques and instrumentation could be assisted by submicron particle reference standards. We propose that high number-density, noble metal (Cu, Ag, Au) particles on silicon, with controlled diameters in the range of 0.02 μm to 0.10 μm, be developed and used as particle reference standards.

Variation in the surface concentration of Fe, Ni, Cu and Zn on Si wafers due to treatment in NH4OH/H2aO2/H2O solution called SC1 is investigated. The metal concentration on the wafer surface depends on the initial surface concentration, concentration in the solution, adsorption probability, desorption rate constant and the treatment time. The surface metal concentration behavior is explained by taking into account the effects of these parameters. The variation in the desorption rate constant with the metal species, the concentration in the solution, treatment temperature and mixing ratio of SC1 is discussed.

This work examines the extent of the deposition of iron on the wafer from (iron) contaminated SC-1 solutions on silicon wafer surfaces, models this effect, and also predicts the chemical state of the iron thus deposited on the wafer surface. The deposition of iron from SC-1 on three different wafer surface terminations was studied. The surfaces were characterized by: (i) the presence of ∼10 Å of native oxide, (ii) by relatively little native oxide and (iii) by a thick thermal oxide. Experiments were performed at room temperature using a 1:1:5 SC-1 (NH4 OH-H2O2-H2O) solution, and also at 80°C with a more dilute composition (0.25:0.5:5). We found that irrespective of the initial surface termination, the amount of iron deposited on the silicon surface from SC-1 exhibited remarkably little deviation over a wide range of spiking levels, leading to the conclusion that in all cases an initial rapid oxidation of the silicon took place, followed by the preferential oxidation of the iron and its inclusion as the oxide into the oxide film. Finally, the model developed predicts that lower temperatures and more concentrated chemistries are more effective in keeping the iron in solution.

In CMOS, the use of epitaxial layers for prevention of latch-up in logic technologies is well-known and pervasive. One of the crucial parameters is the amount of metallic contamination due to transition metals such as Fe in the epi since this phenomena effects both device performance and quality. However, the ability to measure this parameter on product material is not generally available due to inherent problems with most known methods. The limitation of traditional surface photovoltage is that the deep optical penetration of over a hundred microns is well-beyond the depth of most epitaxial layers and does not accurately profile the epitaxial region [1]. In this paper we report on the application of optical surface photovoltage (SPV) using a set of ultra-shallow optical filters to both quantify and qualify as-grown epitaxial layers on CZ P-type silicon. We believe that a non-contact, SPV measurement of Fe concentration and diffusion lengths within an epitaxial region has not been previously reported.

We have investigated crystallographic structures and electrical properties at the interfaces of transition metals such as Ti, Zr, Hf and V and Si(100), from the viewpoint of an application to ohmic contacts in future ULSI's with low contact resistivity and high reliability. We have achieved very low contact resistivities of 3−5×10−8 Ωcm2 for Zr/ and Hf/n+-Si(100) contacts and 1−2×10-7 Ωcm2 for p+-Si at 400–600°C. It is found that the silicidation reaction in this temperature range brings about the formation of deep levels associated with vacancies in Hf/Si and with metal atoms in V/Si. This difference is considered to be related to that in the silicide formation process between these systems. Furthermore, an anomalous electrical characteristics observed for Hf/p-Si contacts has been found to be markedly improved by using a H-termination treatment of Si surfaces.

Time-Dependent Dielectric Breakdown studies were performed on 6.5-, 9-, 15-, 20-, and 22.5- nm thick SiO2 films over a wide range of stress temperatures and electric fields. Very high temperatures (400 °C) were used to accelerate breakdown so that stress tests could be performed at low electric fields close to those used for device operating conditions. The results indicate that the dependence of TDDB on electric field and temperature is different from that reported in earlier studies. Specifically, the electric-field-acceleration parameter is independent of temperature and the thermal activation energy was determined to be between 0.7 and 0.9 eV for stress fields below 7.0 MV/cm.

Failure distributions of high-quality current-generation oxide films are shown to be of single mode and have dispersions that are not sensitive to stress electric field or temperature, unlike distributions observed for oxides examined in earlier studies. These results have implications on the choice of the correct physical model to describe TDDB in thin films. The data also demonstrate for the first time the reliability of silicon dioxide films at very high temperatures.

Next generation ULSI devices will require ultra thin gate insulators where degradation due to contamination or surface microroughness is an even more important problem. Tunneling and breakdown characteristics are critical electrical testing methods, but unfortunately obtaining meaningful oxide integrity information on the one hand and tunneling IV's on the other is a tedious and time consuming process.

In this research, we report on a new method to measure meaningful IV's, Qbd's, and Vbd's at the same time. This method uses a linear current ramp strategy where a voltage ramp to between 8–10 MV/cm is applied first followed by a linear current ramp until breakdown is reached. There are several advantages of this new method: The linear voltage ramp quickly and easily identifies low breakdown devices, whereas switching to a linear current ramp provides for nearly constant field stressing to obtain meaningful IV and Qbd

We have developed a new pre-deposition, remote N2O plasma oxidation treatment for forming nitrided SiO2 films and report here the quality and reliability of devices fabricated with these films. The Si-dielectric heterostructure process has been separated into three independently-controlled steps: i) final Si surface cleaning, and Si – SiO2 interface formation by plasma-assisted oxidation/nitridation at 300 °C; ii) remote plasma-enhanced chemical vapor deposition of nitrided dielectrics, also at 300 °C; and iii) optional post-deposition rapid thermal annealing. This paper focuses on the first step in which the oxidation has been performed with O2, N2O or N2O / O2 mixtures to control the amount of N-atoms at the interface, Nint. We show that the incorporation of up to ∼ 1015 N-atoms/cm2 at the Si-SiO2 interface by this process has no effect on threshold voltage, Vt, or peak channel transconductance, gm,max, but does improve high-field gm and transistor drive current. Improved resistance to Vt and gm,max degradation during hot-carrier stressing of sub-micron devices is also discussed.

Ultra-thin SiO2/Si(111) interfaces have been studied by high resolution x-ray photoelectron spectroscopy. The deconvolution of the Si 2p core-level peak reveals the presence of the suboxide states Si3+ and Si1+ and the nearly complete absence of Si2+. The energy shifts found in the Si 2p and O is core-level peaks arising from charging effects arc carefully corrected. The valence band density of states for ultra-thin (1.8 - 3.7 nm thick) SiO2 is obtained by subtracting the bulk Si contribution from the measured spcctrum and by taking into account the charging effect of SiO2 and bulk Si. Thus obtained valence band alignment of ultra-thin SiO2/Si(111) interfaces is found to be 4.36 ± 0.10 eV regardless of oxide thickness.

We have prepared thin SiO2 layers on Si(100) wafers by electron cyclotron resonance chemical vapour deposition (ECR-CVD) in a multi-chamber ultra-high vacuum (UHV) processing system. The oxides were characterized in-situ by single wavelength ellipsometry (SWE) and x-ray photoelectron spectroscopy (XPS) and ex-situ by Fourier transform infra-red spectroscopy (FTIR), spectroscopic ellipsometry (SE) and capacitance-voltage (CV) electrical measurements. Films deposited at higher pressures, low powers and low silane flow rates had excellent physical and electrical properties. Films deposited at 400 °C had better physical properties than those of thermal oxides grown in dry oxygen at 700 °C. A 1 minute anneal at 950 °C reduced the fast interface state density from 1.2×1011 to 7×1010 eV−1cm−2

Ultraclean semiconductor processes were developed for ULSI technologies to significantly reduce metallics, foreign materials, and to preserve silicon surface morphology. State-of-the-art detection techniques (Elymat, TXRF, VPD, and SPV) were implemented in all critical process sectors. Acceptable levels of metallic contamination were derived from previous experience and from published work on this subject relating metallic contamination levels to gate oxide reliability and retention time.

A comprehensive diagnostic/characterization system was utilized in evaluating a wide variety of test structures emulating key device process interactions. Advanced techniques were employed for measurement of reliability and surface morphology. Also root causes for all integration problems are identified.

A reduced-pressure ultraviolet (UV) photo-oxidation process is described for the removal of organic contamination from Si surfaces with concomitant growth of an ultra-thin oxide passivation layer. As in situ photo-generation of ozone (O3) from dioxygen (O2) is impractical at millitorr pressures, a 2% O3/O2 mixture from an ozone generator is fed to the surface conditioning chamber. UV/O3 surface conditioning employing simultaneous 254/185 nm UV irradiation results in essentially complete removal of carbon contamination in 180 s at 100 mTorr and 100–200°C. Kinetics studies employing cyclohexane-contaminated Si(100) surfaces suggest that carbon removal occurs via two consecutive first-order processes: initial fast photo-oxidation of adsorbed cyclohexane to readily desorbed products and slower photo-oxidation of adsorbed carbonyl intermediates to CO2 and H2O. The activation energies for both processes are 2–3 kcal/mol, consistent with the involvement of photo-generated atomic oxygen species. Self-limiting growth of an ultra-thin oxide passivation layer occurs concomitantly with carbon removal. At saturation, the oxide layer is only 3–4 Å thick, and the growth kinetics are described by a first-order Langmuirian adsorption model.

Hydrogen plasma treatment was used as a cleaning and conditioning step prior to gate oxide deposition in the fabrication of cluster-based MOS field effect transistors. Surface roughness was measured by atomic force microscopy and compared to current-voltage characteristics of the MOSFET devices. The MOSFET devices were evaluated on the basis of threshold voltage, peak mobility, interface scattering, and surface roughness coefficient. Following a 10 minute Hplasma exposure at a substrate temperature of 150°C the rms roughness increased from 1.1±0.3 Å to 17±9 Å. The rms roughness for samples treated for 10 minutes at 700°C was 4±1 Å. Analysis of the MOSFET devices treated in the low temperature range (200°C) show significant degradation due to the H-plasma interaction. Threshold voltage for the devices exposed to a 2 minute H-plasma at a temperature of 200°C was 0.72±0.02 V. In contrast the threshold voltage for the 600°C, 2 minute plasma exposure was 0.86±0.03 V. The peak mobility for those devices was 370 cm2/V-s. Further device analysis was accomplished from the current-voltage measurements to extract a value of interface scattering and surface roughness scattering for each device. Interface scattering and surface roughness scattering do not increase for H-plasma process temperatures of 450 – 700°C. An H-plasma treatment for 2 minutes at 500°C also resulted in no observable increase in rms roughness, a threshold voltage of 0.92±0.03 V, a peak mobility of 410 cm2/V-s, and no increase in interface scattering and surface roughness scattering.

Remote H-plasma and H2/SiH4 plasma processes were studied as potential dry cleaning processes following reactive ion etching (RIE). The processes were compared to a process of UV/ozone followed by an HF dip. The native oxide from Si(100) substrates was removed with an RIE etch of CHF3/Ar. The RIE process produced ∼150Å of a continuous fluorocarbon (CFx) passivation layer on the Si surface. For the post-RIE-cleaning three approaches were studied and compared including (1) uv-ozone exposure followed by an HF dip, (2) remote H-plasma exposure, and (3) remote H2/SiH4 plasma exposure. Auger electron spectroscopy (AES) was used to investigate the surface chemical composition, and AFM was used to measure changes in surface roughness. All three processes showed substantial removal of the passivation layer. The CF× polymer was completely removed in less than 1 min for samples exposed to a 100W remote H-plasma at 15mTorr and 450°C. With the addition of ∼0.1% of SiH4, the remote H2/SiH4 plasma also showed increased removal of residual oxygen contamination. The surface roughness of the plasma processed surfaces increased slightly.

For the analysis of as-cleaned surface, we have used a the unique IR method that uses a highsurface-area porous sample. We have observed by experiments that the oxide growth rate on silicon is reduced to a minimum when the surface is treated with a proper amount of HF vapor obtained from 1% I-IF solution. FTIR and XPS observations of the treated surface suggest that the oxide growth rate is closely related to the amount of the surface fluorides. In UV/O2 cleaning process, we have observed experimentally that addition of water vapor to cleaning gas stream enhances the cleaning efficiency by as much as 1.3 times.

As the size of integrated circuit is scaled down, the importance of Si wafer cleaning has been emphasized. Especially, in the ULSI level device, the cleaning has a great influence on device yields and reliabilities. In this study, we investigate the effects of UV/03 and SCI steps in the HF last cleaning procedures. The UV/O3 and SCI cleaning steps are known to remove the organic contaminants. However, the combination of UV/O3 cleaning step with HF wet chemical solution to remove the metallic impurities has not been studied extensively. We have applied the UV/O3 and SCI steps in the middle of the HF last cleaning procedures and have analyzed Si substrates with TXRF, AFM, I-V, etc. The cleaning splits we applied consist with 4 different types, split 1 (piranha + HF), split 2 (piranha + UV/O3 + HF), split 3 (piranha + SC1 + HF) and split 4 (piranha + UV/O3 + HF repeated 3 times). The contents of metallic impurities were measured with using TXRF and splits 2 and 4 showed low average values of metallic contents. The surface morphologies after each cleaning examined with AFM and the split 3 exhibited rough surface. The electric properties were measured after forming a MOS capacitor with oxide thickness of 250Å. The high leakage current and low breakdown voltage were observed at split 3.

The roughness of the Si/SiO2 interface has a great impact on the electrical properties of the gate-oxide in integrated circuits and consequently it is a large concern for the semiconductor industry. As the thickness of the oxide is decreased, the role of the roughness becomes more critical for the device. The nature of a buried interface prohibits the use of commonly used surface techniques. By the use of crystal truncation rod (CTR) x-ray scattering, it is possible to get information on the termination of the bulk silicon in a nondestructive fashion. The authors have investigated the influence of different cleanings on interfacial roughness using synchrotron radiation-based CTR-scattering. In particular, we looked at silicon(001) wafers both before and after the growth of a 1000Å thermal oxide. The results show that the use of HF during cleaning results in a smoother interface between silicon and its native oxide. Due to smoothing of the interface during the oxidation process, the difference between the various cleaning methods becomes less significant for these thick oxides.