In radiatively heated single wafer reactors, suszeptors are used to control the wafer temperature. This temperature, however, might be significantly different than the suszeptor temperature. The reason is that the conductive coupling of the suszeptor to the wafer is often small, even when the wafer is placed directly on the suszeptor, and the temperature difference is then determined by the optical properties and the spectral distribution of the illumination.

In this paper these temperature differences are calculated with reactor scale simulation for typical geometries. Furthermore the pattern effect is investigated whose magnitude depends on the pattern and the configuration of wafer and suszeptor.

The radiation is modeled with Monte Carlo and the optical properties of the surfaces are calculated from the electromagnetic theory of thin films.

A commercial system with a thick suszeptor for Si-CVD at reduced pressure serves as an example for the size of the discussed effect. The comparison of the simulation with measurements provides a model validation. Then, a typical RTP system equipped with a thin suszeptor is investigated. The configuration is identified under which the thin suszeptor leads to a reduced temperature variation in case of a changing wafer coating and in case of a pattern.

Spectral and spectral band irradiance sensors are developed to measure the spatial heat flux distribution from a rapid thermal processor (RTP) lamp bank. They are used in conjunction with a Sensarray thermocouple wafer to evaluate the thermal uniformity of one axially symmetric lamp bank from a 3 zone RTP system. Measured performance of the lamp bank differs sharply from predictions obtained using a numerical ray trace model. Discrepancies between experimental measurements and model results are resolved by blackening a beveled (focusing) surface introduced to shield process lamp bases from overheating. Further modeling confirms that the bevel causes undesirable focusing of lamp radiation on the planar wafer surface. The shape of the focused component of the irradiance profile is highly dependent on the lamp radiance spatial distribution assumed in the model.

The influence of cooling air and cooling water parameters on the wafer temperature was studied in an RTP system with lamp power control. With a cool down time of 150 seconds between consecutive heating cycles, the wafer temperature in a 1050 °C process was highly sensitive to cooling air flow. With a cool down time of 330 seconds the sensitivity dropped a factor of 5. This was explained through the effect of radiative heat transfer from the quartz to the wafer at higher quartz temperatures (>200 °C). Other factors are variations in the water flow through the oven walls and the repeatability of wafer positioning.

A new temperature compensation concept suitable for rapid thermal processor (RTP) with non-uniform temperature distribution was proposed in this work. Concentric Si rings with different diameters are placed between wafer and planar susceptor and are regarded as a patterned susceptor. By properly arranging the Si rings on the planar quartz or Si susceptor, one can make the semiconductor wafers have more uniform temperature distribution in a non-uniform temperature RTP system. This is a very simple and cheap method for solving the temperature non-uniformity problem in the RTP system.

This paper summarizes a Joint Development Project between SEMITOOL, member company and SEMATECH to demonstrate and develop the fast ramp vertical furnace. The goal of this project was to deliver a production vertical furnace capable of heating and cooling a batch of 50 wafers at average ramp rates of 75 and 50 °C/min, respectively. The furnace did meet these goals. This paper will outline the distinctive and enabling design features of the furnace, such as the use of model predictive control techniques to stabilize the wafer temperatures within 2 to 5 minutes of reaching the nominal target temperature. The test results of a ten run passive data collection for a 145 ohm/sq boron S/D anneal and a 65 angstrom gate oxidation process will be discussed. The boron S/D anneal PDC results exceeded the 3 sigma standard deviation for all points goal of 5.0%. The gate oxidation PDC gave a mean of 65 angstroms and met its 3 sigma standard deviation for all points goal of 4.5%. Using an unyielded model (defect density=0) the cost of ownership is estimated to be $3.02/wafer for a 50 wafer load and as low as $1.68 for a 200 wafers load for a gate oxide process. The fast ramp vertical furnace is designed to meet 0.25 and 0.18 micron technology needs, improve cycle time, and give the customer the flexibility of using different wafer batch sizes within a 25” flat temperature zone (where the ramp rates are adjusted according to the wafer pitch).

Batch thermal processing satisfies device requirements for 0.5μm and larger technology nodes for silicon semiconductor manufacturing and continues to satisfy these requirements as feature sizes decrease beyond 0.5μm to 0.35μm. At the transition from 0.35μm to 0.25μm, source/drain (S/D) anneal, TiSi form, and TiSi anneal require rapid thermal processing (RTP) because of improvements in thermal budget, lateral dopant diffusion, and in silicidation, with RTP. RTP and rapid thermal chemical vapor deposition (RTCVD) become enabling technology for devices at 0.25μm and smaller technology nodes.

A cost of ownership (CoO) analysis provides a comparison between the financial impact of alternatives and helps in determining the lowest cost answer for that process, assuming all other process parameters can be met equally by all alternatives. This report analyzes primary cost drivers, their importance within each analysis, and potential for improvements which may cause a significant change in CoO values at 200mm.

Fast-ramp small-batch vertical furnace technology improves batch furnace processing capabilities. Reducing cycle time and improving diffusion control while still maintaining a low cost of ownership and film thickness uniformity are the key benefits of this new technology. A new high power density furnace has been designed to accommodate accelerated wafer temperature ramp up and cool down rates. Unique quartz fixturing is also used to minimize thermal stress across the wafers. This paper will describe both thermal uniformity and film uniformity results for a 65Å Gate Oxide Process for the Rapid Vertical Processor (RVP). In addition, thermal stress data and throughput results will be presented.

The evolution of integrated single-wafer processing for high-temperature applications in the front end of the line (FEOL) occurred with the advancements in single-wafer rapid thermal processing and its acceptance as a manufacturing technology. The Integra RTCVD cluster tool for high-temperature applications features wafer cleaning, rapid thermal processing and single wafer chemical vapor deposition steps. The paper presents integrated vapor phase clean and RTCVD applications for FLASH memory gate stack and DRAM cell.

A single wafer gate cluster tool has been evaluated in an effort to quantify the effects of gate clustering on defect density, process capability and device performance. The single wafer gate cluster tool consists of a hydrofluoric vapor (HF-vapor) pre-gate cleanup module, a rapid thermal oxidation (RTO) module and a polysilicon rapid thermal chemical vapor deposition (RTCVD) module. The gate dielectric charge to breakdown (Qbd) of capacitor structures formed using the integrated single wafer gate cluster tool process sequence typically averaged 9.1 to 12.3 coulombs per square centimeter (C/cm2). Excellent gate oxide integrity yield values in the range of 99.8% to 100% were also routinely obtained. The films were free of low field and mid field gate dielectric breakdown events and the devices exhibited dielectric breakdown field strength in excess of fourteen megavolts per centimeter (MV/cm). The cluster tool process was successfully integrated into a transistor device flow. The characteristics of devices formed using the cluster tool process were equivalent to those of devices formed using conventional batch processing at the gate level.

The purpose of this publication is to give an insight into process development performed in two modules which belong to a cluster tool designed for the gate stack process sequence of cleaning, gate oxidation, and polysilicon chemical vapor deposition. For the first time, following the hardware and software MESC-based standards, two suppliers have integrated complementary modules to build a cluster tool. This equipment answers the demands of the 1C Manufacturers and follows the “best of breed” approach. Four single wafer rapid thermal process chambers, a Vapor Phase Cleaning (VPC) and a Rapid Thermal Oxidation/Nitridation (RTO/N) module from STEAG-AST Elektronik, a polysilicon and a nitride chemical vapor deposition module from ASM International are currently connected together to prove the feasibility of the single wafer processing gate stack cluster tool.

A cleaning process using anhydrous HF (AHF)/methanol and ozone is carried out in a STEAG-AST Vapor Phase Cleaning module (VPC). This module is integrated in a state-of-the-art cluster tool also consisting of a STEAG-AST Rapid Thermal Oxidation module (RTO). The dependence of AHF vapor phase etch rate of thermally grown silicon dioxide on different process parameters, such as etch time, AHF-flow, and temperature is evaluated. The optimized etch process is found to be at a temperature of 40°C and at a pressure of 50 mbar for this VPC module. Using the above etch parameters various combinations of vapor phase surface preparation chemistries combining AHF etching and ozone/UV cleaning are evaluated.

To demonstrate the feasibility of this cluster tool for advanced gate dielectric formation, 4.0 nm thin oxide is grown directly after the cleaning in the RTO module without breaking the vacuum. Time dependent dielectric breakdown results for oxides pre-oxidation-cleaned in AHF, and in AHF followed by ozone are compared to a reference sample without any dry pre-oxidation cleaning. It can be shown, that the cleaning in AHF with a subsequent ozone step at 200°C under UV light leads to improved breakdown characteristics compared to AHF/methanol cleanings without such subsequent ozone/UV step or conventional wet cleaning using HF-Dip.

Two types of real-time oxygen monitoring are investigated for RTP applications, i.e. addressing the basis for a state-of-the-art clean ambient technology and understanding its impact on real processes. Diagnosing of gas flow dynamics in the chamber is carried out by tracer experiments. Deviation from plug flow, which decreases purge efficiency, is found to be a function of gas flow rate. The monitoring of a typical two-step RTP process for silicidation of Ti or Co show that both adsorption and desorption take place. Oxygen is desorbed first at lower temperatures (during temperature ramp) then starts to be adsorbed at higher temperatures. In the case of Ti, a few monolayers of oxygen is adsorbed during the first RTP but less oxygen is adsorbed during the second RTP. The amount of oxygen adsorbed during Co RTP is found to be not as high as during Ti RTP.

The formation of TiSi2 was compared over samples implanted with arsenic and BF2 at different doses and annealed at different temperatures and lengths of time in a rapid thermal process. Measurements were done to determine the composition and thickness of the suicide formed. The composition was determined from Auger electron spectroscopy, Rutherford backscattering spectroscopy, and transmission electron microscopy. The phase formation of the suicide was characterized by X-ray diffraction. Dopant redistribution was studied using secondary ion mass spectroscopy. Comparing the results of the different implant doses we found that the amount of suicide formed over heavily doped Si at formation temperatures of 600°C to 650°C was reduced compared to undoped Si. At formation temperatures above 750°C the implanted dose and species did not significantly affect the amount of suicide formation. Above 750°C the TiSi2 structure was found to be the C54 phase. Arsenic was found to diffuse into the Ti suicide layer in a diffusion controlled process. Boron was found to accumulate at the Ti suicide interfaces both with the substrate and with the surface TixOyNz layer.

Suicide formation during thermal annealing of thin Pt layers deposited by evaporation onto crystalline silicon substrates was studied by in-situ spectral ellipsometry. As was shown in an earlier study, Pt suicide is formed in a two-step process with intermediate stages of Pt2Si and PtSi at temperatures of about 190 and 240 °C, respectively. We observed a shift of about 15 °C of the di- and monosilicide formation, when the anneal rate was lowered from 3 to 1 K/min. The analysis of the reaction kinetics using the normalized ellipsometric angle δ yields a good fit to the data for different anneal rates with an activation energy of (1.6 ± 0.2) eV. The underlying model of suicide formation through a multilayer system was checked with depth profiles and compositional information obtained from Rutherford Backscattering.

In this paper, we describe the results of recent work in which TiSi2 formation on deep-submicron polysilicon gates is achieved using pulsed excimer laser irradiation. Formation of low resistivity titanium suicide on sub-0.1 μm polysilicon lines is confirmed by sheet resistance measurements. High-resolution TEM examination shows exceptionally smooth interface between suicide and heavily-doped silicon substrate. Gate to source/drain bridging is not observed. Analytical techniques including Rutherford backscattering spectroscopy (RBS) and X-ray diffraction (XRD) have been used to characterize the irradiated films. This laser-assisted suicide formation process is a promising technology for extreme submicron MOSFET applications.

RTP will be replaced with some of the conventional thermal processing employed in ULSI fabrication lines in near future. We show at first the device characteristics demanded for next generation DRAM which is a typical example of ULSIs and some issues to satisfy the demands. Next we show some candidates for RTP in the ULSI processes and discuss difference between RTP and the conventional thermal processes. We think one of the largest difference is the quenching Si wafers after short time annealing and by the quenching the deep levels due to fast diffusing atoms and point defects in Si are introduced. Experimental results of N2 and Cu related deep levels are shown as the examples of the deep levels induced by the quenching in Si. Finally, we propose the gettering method for them in RTP.

Vacancy-type defects in Si crystals introduced by ion implantation have been investigated by an energy-variable positron beam The present paper describes the general feature of point defects induced by ion implantation from the point of view of their dependence on implanted ion species, ion dose, ion energy, implanted targets, thermal after implantation, the presence of oxide overlayers and so on.

2. 0 keV 11B+, 2.2 keV 49BF2+ ion implanted and 1.0 kV Plasma Doped (PLAD) wafers of a dose of 1E15/cm2 were annealed at various times and temperatures in a variety of ambiente: 600 to 50,000 ppm O2 in N2; 5% NH3 in N2; N2O; N2 or Ar, in order to investigate the effects of the annealing ambient on the formation of ultra-shallow junctions. RGA data was collected during some (if the anneals to assist in identifying the complex surface chemistry responsible for boron out-diffusion. Subsequent to the anneals, ellipsometric, XPS, four-point probe sheet resistance and SJJVIS measurements were performed to further elucidate the effects of the different ambients on the r etained boron dose, the sheet resistance value, the RTP grown oxide layer and the junction depth. In the cases where oxygen was present, e.g. N2O and O2 in N2, an oxidation enhanced diffusion of the boron was observed. This was most dramatic for the N2O anneals, which at 1050°C 10s diffused the boron an additional 283 to 427 Å, depending on the particular doping condition and species. For the case of BF2 implants and PLAD, anneals in 5% NH3 in N2 reduced the junction depth by a nitridation reduced diffusion mechanism. RGA data indicated that the out-diffusion mechanisms for B and BF2 implanted wafers are different, with the BF2 exhibiting dopant loss mechanisms during the 950°C anneals, producing F containing compounds. B implants did not show doping loss mechanisms, ais observed by the RGA, until the 1050°C anneals and these signals did not contain F containing compounds. Equivalent effective energy boron implants of 8.9 keV BF2 vs. 2.0 keV B, however, indicated that the overall effect of the F in the BF2 implants is very beneficial in the creation of ultra-shallow junctions (compared to B implants): reducing the junction depth by 428 Å, and increasing the electrical activation (determined by SRP) by 11.7%, even though the retained dose (resulting from an increased out-diffusion of B), was decreased by 5.4%.

Up to now, kinetic effects in rapid thermal processing (RTP) have been assessed using the concept of thermal budget, with the idea that thermal budget minimization should minimize dopant diffusion and interface degradation. This work highlights shortcomings with that principle. Experiments comparing directly the rate of Si chemical vapor deposition with that of dopant diffusion show how thermal budget minimization can actually worsen diffusion problems rather than mitigate them. We present a straightforward framework for improving the results through comparison of activation energies of the desired and undesired phenomena. This framework explains the experimental results and provides strong kinetic arguments for continued development of rapid isothermal processing and small batch fast ramp methods.

Power devices often contain very deep boron diffusions extending through the thickness of the wafer to create junction isolation. In this paper we first report our investigations to replace the standard solid-state deep diffusion, with Temperature-Gradient Zone Melting (TGZM). During TGZM, a molten silicon/aluminium solution moves through a Si wafer in minutes, leaving a highly Al doped trail behind it. The liquid phase diffusion is driven by the vertical thermal gradient created in the wafer by a properly designed RTP.

On the other hand, for the purpose of high voltage (> 400V) smart power applications, substrates with localised and thick SOI layers are needed. We also present a method for recrystallization of thick poly silicon films by Lateral Epitaxial Growth over Oxide (LEGO), using a similarly designed RTP.

The two processes, that is LEGO and TGZM, use a Rapid Thermal Processor and are compatible. The RTP is specially designed to create a thermal gradient perpendicular to the wafer surface.