Valence mending of a semiconductor surface, such as the Se-passivated Si(001) surface, improves the chemical and thermal stability of the surface as compared to the bare Si(001) surface. In this paper, we report the suppression of Ni silicide formation between Ni and Si(001) through monolayer passivation of Si(001) by Se. Ni was deposited on both Se-passivated and bare Si(001) surfaces. The samples were annealed at temperatures from 400°C to 700°C. Cross-sectional TEM (Transmission Electron Microscopy) revealed that Ni on bare samples reacted with Si at 400°C and formed silicide, whereas Ni on Se-passivated samples did not react with Si at 500°C. Surface composition analysis by XPS (X-Ray Photoelectron Spectroscopy) showed pure Ni surface on Se-passivated samples annealed at 400°C and 500°C, but silicide surface on bare samples annealed at the same temperatures. Hence, Se passivation suppresses the formation of Ni silicide on the Si(001) surface by over 100°C as compared to the bare Si(001) surface. These results may have important implications in source/drain engineering in sub-100 nm Si CMOS (Complementary Metal Oxide Semiconductor) devices.

A novel Differential Hall Effect technique is used to obtain doping profiles of 2keV implants of antimony in <100> silicon at a depth resolution of 2nm. The electrical profiles are compared with atomic profiles determined from Secondary Ion Mass Spectroscopy (SIMS) measurements. We demonstrate good consistency between the two profiling techniques and confirm that the SIMS profiles can be used to identify the junction depth. The profiles show that antimony does not diffuse significantly for annealing temperatures below 800°C.

The next generation of Si devices requires thermal treatments of 1200°C – 1300°C but can only withstand temperatures above 800°C for a few milliseconds. Current rapid thermal processing techniques cannot meet these requirements. We have designed, constructed, and tested a microwave reactor that heats Si to 1300°C in only a few milliseconds and cools the wafer at a rate that exceeds a million degrees per second. Applying millisecond microwave annealing to ultra-shallow junction formation in advanced Si devices shows that this technique meets or exceeds the thermal processing requirements for the next several generations of Si devices.

The relaxation processes of strained silicon films on silicon-rich relaxed SiGe alloys have been studied. Experimental structures were generated via Molecular Beam Epitaxial (MBE) growth techniques and contain a strained silicon capping layer of approximately 50 nm. The relaxed SiGe alloy compositions range from 0 to 30 atomic% germanium. Samples received two distinct types of silicon implants. A 12 keV Si+ implant at a dose of 1×1015 atoms/cm2 was used to generate an amorphous layer strictly confined within the strained Si cap. An alternate 60 keV Si+ implant at a dose of 1×1015 atoms/cm2 was employed to create a continuous amorphous layer extending from the sample surface to a position 50 nm into the bulk SiGe material. The strain relaxation and regrowth processes are quantified through High Resolution X-Ray Diffraction (HRXRD) rocking curves and Cross-sectional Transmission Electron Microscopy (XTEM). The role of injected silicon interstitials upon the strain relaxation processes at the Si/SiGe interface after annealing at 600°C is investigated.

Beyond its applications in silicon MOSFETs, cobalt disilicide is potentially useful for the formation of epitaxially overgrown quantum dots and quantum wires. We report the formation of cobalt silicide on Si (100) and its overgrowth by silicon. Cobalt films approximately 3.5 nm in thickness have been deposited on Si (100) using a cobalt carbonyl organometallic source. We observe by reflection high-energy electron diffraction (RHEED) that the deposited cobalt film is converted to epitaxial cobalt disilicide upon annealing at 850°C, considerably higher than the silicidation temperature typically observed for sputtered cobalt. We explain this behavior with the aid of secondary ion mass spectrometry (SIMS) profiling of the carbon and oxygen impurity concentrations. The cobalt disilicide layers have been overgrown with silicon at 625°C. We contrast the surface topology measured by atomic force microscopy (AFM) just after cobalt growth, after silicidation, and after overgrowth with silicon. The surface has been observed to be rough after growth of silicon by silane exposure for 15 min at 625°C at 0.55 mTorr of chamber pressure. The surface roughness prevails even after overgrowing with silicon for 60 min at same chamber temperature and pressure conditions.

Thermal wave (TW) studies of ultra-shallow junctions (USJ) formed by ion implantation into a semiconductor wafer followed by rapid thermal annealing (RTP) are described. It is shown that using the TW technique allows for a simultaneous determination of the most important USJ parameters – depth and profile abruptness. Experimental results for junction depth and abruptness obtained on a set of B+-implanted, RTP-annealed USJ samples show better than 0.99 correlations to the corresponding secondary ion mass spectroscopy (SIMS) data.

Using density functional theory calculations within the generalized gradient approximation, we have investigated the structure, energetics, bonding, and diffusion behavior of Si interstitials and boron-interstitial pairs at the Si/SiO2 interface. We find that interstitials are significantly stabilized at the Si/SiO2 interface and prefer to reside on the SiO2 side rather than the Si side. Due to the interstitial stabilization, boron-interstitial pairs are likely to be easily dissociated in the vicinity of the Si/SiO2 interface. This study provides valuable insight into interstitial annihilation and boron precipitation at the interface.

The relationships between Boron Interstitial Cluster (BIC) evolution and boron diffusion in relaxed Si0.8Ge0.2 have been investigated. Structures were grown by Molecular Beam Epitaxy (MBE) with surface boron wells of variant composition extending 0.25 [.proportional]m into the substrate, as well as boron marker layers positioned 0.50 [.proportional]m below the surface. The boron well concentrations are as follows: 0, 7.5×1018, 1.5×1019, and 5.0×1019 atoms/cm3. The boron marker layers are approximately 3 nm wide and have a peak concentration of 5×1018 atoms/cm3. Samples were ion implanted with 60 keV Si+ at a dose of 1×1014 atoms/cm2 and subsequently annealed at 675°C and 750°C for various times. Plan-view Transmission Electron Microscopy (PTEM) was used to monitor the agglomeration of injected silicon interstitials and the evolution of extended defects in the near surface region. Secondary Ion Mass Spectroscopy (SIMS) concentration profiles facilitated the characterization of boron diffusion behaviors during annealing. Interstitial supersaturation conditions and the resultant defect structures of ion implanted relaxed Si0.8Ge0.2 in both the presence and absence of boron have been characterized.

The effect of boron concentration on boron-interstitial cluster (BIC) dissolution was studied in separation by implantation of oxygen (SIMOX) and SOITEC silicon-on- insulator (SOI) materials. SOI substrates having surface silicon thickness of 750 Å and 1450 Å were ion implanted with 11B+ at a energy of 15 keV. The dose of the implant was varied from 3×1014 cm−2 to 1×1015 cm−2 to provide different boron peak concentrations. Anneals were performed at 825 °C in a nitrogen ambient using RTA for short times and furnace anneals for longer times. The retained dose of boron in the surface silicon layer was estimated using simulations from UT-Marlowe 5.0. Hall Effect was used to measure the sheet resistance, mobility, sheet number, and fraction of active boron. At lower concentrations, SOI exhibited significantly lower sheet numbers. As the boron concentration was increased SOI began to approach bulk Si. However, degraded mobility and sheet resistance was observed at all concentrations. Truncating the boron profile over the surface Si/buried oxide interface enhanced the fraction of active boron in the 750 Å SOI. This also lead to a higher fractional activation in 750 Å SOI than bulk Si as the concentration increased due to a loss of interstitials, effectively reducing the BIC population.

In this work was investigated a simple laser doping method employing doped oxide glass films as dopant source (up to 2.1021cm−3) which are deposited onto silicon by the spin coating technique. Both short (20 ns) and long (200 ns) pulse duration excimer laser beams were used to deposit a large amount of energy in a short time onto the near-surface region. Under suitable conditions, the irradiation leads to surface melting and dopant incorporation by liquid phase diffusion from the surface. Boron distribution profiles in the two pulses duration regimes were studied as well as their electrical properties, and the junction formation of less than 20 nm in depth was demonstrated.

A theoretical study of edge dislocation locking by impurities in silicon is presented. Three groups of impurities are considered: (i) light atoms O, N, and C., (ii) large atoms Ga, and Ge, and (iii) small dopant atoms B, P, and Al. Based on impurity size effect model, these three groups produce distinct different dislocation locking effects. Atoms from the first group strongly bind with edge dislocations. The O, N, and C atmospheres are similar, with a slightly stronger occupancy probability for O and N in the vicinity of the dislocation core. For the second group, Ge loosely binds to dislocation and resists at most 1/3 of the separation shear stress that the first group can withstand. Germanium has only a small chance to reach the dislocation core. The third impurity group does not resist shear any separation stress from edge dislocations. Moreover, B and P atoms can not be trapped at all by edge dislocations. At a local atomic fraction of 10−4, edge dislocation-impurity binding energy varies from 0.008 eV/Å for P to 1.7 eV/Å for N and 1. 8 eV/Å for O. In addition, using molecular mechanics on system of 34552 atoms the self-energy of an edge dislocation was calculated and found equal to 156 meV/Å.

We demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2 for Source/Drain, reduces the junction leakage by two decades.

Making use of SPER (Solid Phase Epitaxial Regrowth) As and B deep source/drain junctions with high activation can be obtained at temperatures below 700°C. However, higher thermal budget is required to regrow and activate the dopants in the poly gates. Low junction leakage and low contact resistance can be obtained for Ni-silicided As and B SPER junctions making use of deep As and B implants. Because of the low thermal budget source/drain junctions obtained by SPER are an attractive alternative to conventional spike annealed junctions for technologies making use of metal gates.

Pattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm <100> silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

Nickel monosilicide (NiSi) is a leading contender to replace the currently used class of silicides for contacts to the source, drain and gate regions in Complimentary Metal-Oxide- Semiconductor (CMOS) circuits. In this work, the effect of substrate hydrogenation by a hydrogen plasma treatment prior to nickel deposition and silicidation was studied. The sheet resistance of the silicide film shows a significant decrease under hydrogenation of the Si substrate prior to Ni evaporation/anneal for projected silicidation temperatures below 600°C. Correspondingly, the Si region near the interface is decorated with defects. At higher silicidation temperatures, the sheet resistance rises along with greater in-diffusion of Ni into the hydrogenated Si samples. Secondary Ion Mass Spectrometry, Transmission Electron Microscopy and Hall effect measurements are used to characterize the samples.

We have investigated and modeled the diffusion of boron implanted into crystalline silicon in the form of boron difluoride BF2+. Low energy BF2+ 1×1015 cm−2 implantations at 2.0keV were characterized using Secondary Ion Mass Spectrometry (SIMS) in order to measure dopant profiles. RTA was carried out at 950°C, 1000°C, 1050°C and 1100°C during 10s, 20s, 30s and 60s. The results show that concentration profiles for BF2+ implant are shallower than those for a direct B+ ion implantation. This could be attributed to the presence of fluorine which trap interstitial Si so that interstitial silicon supersaturation is low near the surface.

Equilibrium geometries and formation energies of neutral and charged In complexes with silicon native defects (vacancy (V) and self-interstitials (I)) and with C impurities are investigated within density functional theory, using the Vienna Ab-initio Simulation Package. We determine formation energies and ionization levels of different complexes and discuss the contribution of I and V to indium diffusion. We also identify the In-C defect responsible for the increased electrical activation in In+C-doped silicon samples. The ab initio energetics is then implemented in a continuum diffusion code in order to simulate the diffusion of as-implanted In profiles under different thermal treatments.

In this paper, we present a new set of conditions which can be used for imaging {113} defects. These conditions have the advantage of allowing the simultaneous imaging of all the variants of the defects. They can be used for building up accurate size-histograms or for checking the occurrence of the different variants. Making use of these conditions, we revisit the well- known experiments of the dissolution of the {113} defects and pinpoint some specific features of defect evolution during annealing which were not evidenced in previous works. The new results are discussed and are definitely found to be well-explained in the framework of a non- conservative Ostwald ripening.

Nitrogen doped silicon samples were irradiated with 200 kV electrons in a transmission electron microscope (TEM). The resulting room temperature point defect creation, bonding and segregation were studied by in situ conventional and Z Contrast TEM imaging and electron energy loss spectroscopy (EELS). Energy loss spectra from areas attributed to be rich in vacancies or silicon self-interstitials are found to be significantly different from the bulk in the near-edge structure of their Si-L2,3 edges. The experimental results are compared with ab initio density of states calculations for electronically excited atoms near relaxed point defect structures and plans are outlined to extend this technique to individual point defect characterization.

Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions.