The critical adhesion energy of benzocyclobutene (BCB)-bonded wafers isquantitatively investigated with focus on BCB thickness, material stack andthermal cycling. The critical adhesion energy depends linearly on BCBthickness, increasing from 19 J/m2 to 31 J/m2 as theBCB thickness increases from 0.4 μm to 2.6 μm, when bonding silicon waferscoated with plasma enhanced chemical vapor deposited (PECVD) silicon dioxide(SiO2). In thermal cycling performed with 350 and 400 oC peak temperatures,the significant increase in critical adhesion energy at the interfacebetween BCB and PECVD SiO2 during the first thermal cycle isattributed to relaxation of residual stress in the PECVD SiO2layer. On the other hand, the critical adhesion energy at the interfacebetween BCB and PECVD silicon nitride (SiNx) decreases due to theincrease of residual stress in the PECVD SiNx layer during thefirst thermal cycle.

Increasing demands for faster chip speed and reduced power consumption aredriving the semiconductor industry to develop insulating layers with lowerdielectric constants. As the dielectric constant of a material is reduced,however, it becomes increasingly difficult to achieve the mechanicalstrength required to manufacture a multilevel interconnect. A new route tothe synthesis of mesoporous silica has been demonstrated on 200 mm wafers.Silicate precursors dissolved in supercritical CO2 are infusedinto a block copolymer film. The polymer is then removed, but the resultingporous SiO2 replicates its ordered structure, enhancing thestrength of the network. Incorporation of alkyl silicates further improvesthe film properties. Post-treatment to cap residual silanol groups rendersthe surface of the film hydrophobic and stabilizes it to air exposure. Byappropriate choice of the block copolymer and other process parameters, thepore size and density can be varied and k values as low as 1.8 can beachieved. For a film with a dielectric constant of 2.25, the pore size is ∼4nm. The hardness and modulus are 1.1 GPa and 7.8 GPa, respectively, asmeasured by nanoindentation. Four-point bend measurements yield fractureenergies of 9.8 J/m2. More importantly, the film can withstandchemical mechanical planarization (CMP) using standard oxide polishingconditions.

Spin-on Low-K materials are potentially very attractive as interconnectionmaterials in a wide range of semiconductor structures. In this work, neworganic-inorganic hybrid materials synthesized by vinylsilane polymerizationwere proposed. According to compositions and additional fabrications,dielectric constants of these materials were evaluated to be 2.3∼3.1. Thehardness was 2.0GPa after 430°C curing. These materials had good adhesionstrength such that fracture toughness on silicon wafer was 0.22 MPam0.5 without any adhesion promoters. This result indicatesthat these organicinorganic hybrid materials are very promising candidatesfor low-K dielectrics.

The film properties of two PECVD deposited dielectric copper barrier filmshave been optimized to improve BEOL device reliability in terms ofelectromigration. Two critical aspects that affect electromigration are thedielectric barrier film hermeticity and adhesion to copper. We use a methodto quantify the barrier film hermeticity and have optimized the hermeticityof the BLOκ™ low-κ dielectric barrier film to be similar to that of siliconnitride. By using FT-IR we find that the film porosity has a much strongereffect than the film stoichiometry on hermeticity. In addition, theinterfaces between Damascene Nitride™ with copper, as well as BLOκ withcopper have been engineered to improve the interfacial adhesion energy to>10 J/m2 for both Damascene Nitride and BLOκ.

Silicon is the dominating material for the fabrication of MEMS devices,especially in high volume production. However, metals with their typicalproperties are used to enhance or enable the functionality of MEMS. Incontrast to microelectronic technologies, not only the electrical but alsothe mechanical and optical behavior of metals could be helpful. Newrequirements in MEMS technologies demand optimized processes inmetallization for the fabrication of microstructures.

This paper presents some metallization applications and related technologydevelopment in the field of MEMS.

Polymerization occurring during fluorocarbon plasma treatment as a potentialmethod for pore sealing was investigated. CHF3 was used as areactant gas to expedite the rate of polymerization due to the presence ofhydrogen and the low C/F ratio. The reactor pressure was varied from 30mTorrto 90mTorr to change the number of neutrals that act as the polymerizingspecies. The films were exposed to the plasma for times of 1min, 3min, and 5min to observe the penetration depth of neutrals and the thickness ofmodified layer as a function of time. Dielectric constants were measuredbefore and after plasma treatment. The film morphology was investigated byscanning electron microscopy before and after plasma treatment and afeatureless surface morphology was observed at 90mTorr on a 56% porosityfilm. After plasma treatment, the average pore neck size decreases which mayhelp reduce metal precursor penetration during metallization.

Supercritical fluids (SF) have been used in a wide variety of applications:in industrial processes, analytical, waste detoxification, etc. Recently,its usefulness extends to the semiconductor industry. Researches have shownthat supercritical CO2 (SCCO2) can be used to removephotoresists and significantly reduce the amount of waste from solvents incomparison to conventional stripping techniques. SF will also find itsusefulness in cleaning high aspect ratio vias and deep trenches assemiconductor features shrink to submicron levels. We will report here theuse of supercritical CO2 treatments in extraction of porogensfrom a nanohybrid film fabricated via templated-porogen approach. Its use asa medium to repair the damage in porous films from plasma ashing will alsobe presented. The ability to tune the solvation and diffusion power of SCCO2 and to swell the film matrix make it a good medium forsilylation to restore hydrophobicity and functionalize the film.

We have developed a novel microwave near-field scanning probe technique fornon-contact measurement of the dielectric constant of low-k films. Thetechnique is non-destructive, noninvasive and can be used on both porous andnon-porous dielectrics without any sample preparation. The probe has afew-micron spot size, which makes the technique well suited for real timelow-k metrology on production wafers. For dielectrics with k<4 theprecision and accuracy are better than 2% and 5%, respectively. Results forboth SOD and CVD low-k films are presented and show excellent correlationwith Hg-probe measurements. Results for k-value mapping on blanket 200mmwafers are presented as well.

Stress-induced void formation (SIV) was studied in dual damascene Cu/oxideand Cu/low k interconnects over a temperature range of 140 ∼ 350 °C. Twomodes of stressmigration were observed depending on the baking temperatureand sample geometry. At lower temperatures (T < 290 °C), voids wereformed under the periphery of via connecting to narrow lines. This mode ofstressmigration showed a typical behavior of stressmigration with peakdamage at 240 °C, and an activation energy (Q) of 0.75 eV for Cu/oxideinterconnects. At a higher temperature range (T > 290 °C), voids werefound in via bottoms which were connected to wide lines. The rate of hightemperature stressmigration increased exponentially with temperature up to350 °C and did not show a peak at a certain temperature. The activationenergy was 1.0 eV for Cu/oxide, 0.86 eV for Cu/OSG, and ∼1.0 eV for Cu/FSGinterconnects. The dependence of stressmigration on linewidth, samplegeometry, and ILD material is presented in this paper.

A convenient nanoscratch method was combined with atomic force microscope(AFM) and transmission electron microscope (TEM) observations to conduct thefirst-ever evaluation of the adhesion strength of a complicatedmicrostructureCu/Ta/TaN/pSiO2/low-k/SiC/pSiO2/Si-substrate with theaim of correlating the fracture strength with the results of chemicalmechanical polishing (CMP) tests. Concretely, this evaluation focused on thefact that specimens having a low-k layer pretreated with rare-gas plasmaprior to the deposition of the SiO2 layer exhibited lowdelaminated densities in the Cu CMP process. It was found that a specimenwith the rare-gas plasma pretreatment exhibited a higher frictioncoefficient, a higher critical load and brittle adhesive failure resultingfrom delamination at the interface between the low-k and SiC layers. Aspecimen without the rare-gas plasma pretreatment displayed a lower frictioncoefficient, a lower critical load, and ductile cohesive failure in thelow-k layer. Because less plastic deformation was observed in the low-klayer subjected to the rare-gas plasma pretreatment, it is assumed that thepretreatment reinforced the mechanical properties of the low-k layer, makingit more resistant to ductile cohesive failure. These results agreed with theCMP test data and indicated that the nanoscratch method makes it possible topredict the ability of complicated Cu/low-k interconnect structures towithstand the CMP process.

Three terminal ‘dotted-I’ interconnect structures, with vias at both endsand an additional via in the middle, were tested under a variety of testconditions. Failures (mortalities) were observed even when segments weretested under conditions that would not have led to failure in two-terminalstructures. Mortalities were found in right segments with jL values as low as 1250 A/cm, which is lower when compared to theimmortality condition (jL)cr of 3700 A/cm reported for similar via-terminated structures.Moreover, we found that the mortality of a dotted-I segment is dependent onthe direction and magnitude of the current in the adjacent segment. Theseresults suggest that there is not a definite value of the jL product that defines true immortality in individual segmentsthat are part of an interconnect tree. More importantly, the critical jL value for a single segment of Cu interconnects may be reducedor increased by an adjacent segment. Therefore independently determined (jL)cr values cannot be directly applied tointerconnects with branched segments, but rather the magnitude as well asthe direction of the current flow in the adjoining segments must be takeninto consideration in evaluating the immortality of interconnect segments inan interconnect network.

Dry etching of silver for the metallization in microelectronics isinvestigated. Etching is performed using an electron-cyclotron-resonancereactive-ion-beam-etching system (ECR-RIBE) in an Ar/CF4 or Ar/CF4/O2 mixture. The etch characteristics arestrongly affected by ion energy (beam voltage and microwave energy); the O2 concentration in the reactive mixture has only a smalleffect. An anisotropic, smooth etch profile and clean surface are obtained.Focused ion beam (FIB) and atomic force microscopy (AFM) have been used tostudy the etched profile and the roughness, respectively.

An unexpected mode of plastic deformation was observed in damascene Cuinterconnect test structure during an in-situ electromigration experimentand before the onset of visible microstructural damages (void, hillockformation). We show here, using a synchrotron technique of white beam X-raymicrodiffraction, that the extent of this electromigration-inducedplasticity is dependent on the line width. The grain texture of the linemight also play an important role. In wide lines, plastic deformationmanifests itself as grain bending and the formation of subgrain structures,while only grain rotation is observed in the narrower lines. This earlystage behavior can have a direct bearing on the final failure stage ofelectromigration.

The physical and electrical properties as well as thermal stability ofreactively sputtered titanium nitride (TiN) film serving as a diffusionbarrier was studied for silver (Ag) metallization. The thermal stability ofAg/TiN metallizations on Si with 12-nm-thick TiN barriers, as-deposited andafter annealing at 300-650°C in N2/H2 for 30 min, wasinvestigated with sheet resistance measurement, X-ray diffraction, focusedion beam-scanning electron microscopy, atomic force microscopy and X-rayphotoelectron spectroscopy. According to electrical measurement no change ofsheet resistance was found after annealing at 600°C, but an abrupt riseappeared at 650°C annealing. There are two causes by which the Ag/TiN/Sistructure became degraded. One is agglomeration of the silver layer, and theother is oxidation and diffusion which are also associated problems duringthermal annealing.

Sub-lithographic copper damascene lines were fabricated to investigatealready today the physical phenomena and scaling limits of metallicconductors in the metallization systems of chip generations which arebelieved to be in production 10 years from now and later. Using standardmanufacturing processes and state-of-the-art process tools, includingstandard lithography tools, narrow copper lines were fabricated at theexpense of a relaxed pitch by use of a removable spacer technique. Thesecopper nano interconnects were passivated and subjected to electricalmeasurements. Our results show that continuous down scaling to increasedevice performance will result in an unfavorable increase of the electricalresistivity of copper in stateof-the-art metallization schemes. Electricalmeasurements over a wide range of temperatures down to cryogenictemperatures reveal the limited potential of cooling to reduce resistivityof conductors as lateral dimensions will be shrinked down to the sub-100nmregime. By down scaling of copper diffusion barriers in damascene trenches,barrier functionality was demonstrated after high temperature anneals andexcessive bias-temperature stress tests for films meeting or even exceedingend-of-roadmap thickness requirements. An analysis of the temperaturedependence of the leakage current measured at very high electric fieldsapplied between neighboring damascene lines suggests the conductionmechanism in the SiO2 used as intermetal dielectric to beFrenkel-Poole type rather than Schottky emission. Electromigration lifetimes of sub-100nm copper lines embedded in oxide were found to becomparable with those obtained for similar structures fabricated withtoday's feature sizes.

State-of-the-art ICs for microprocessors routinely dissipate power densitieson the order of 50 W/cm2. This large power is due to thelocalized heating of ICs operating at high frequencies, and must be managedfor future high-frequency microelectronic applications. Our approachinvolves finding new and efficient thermally conductive materials.Exploiting carbon nanotube (CNT) films and composites for their superioraxial thermal conductance properties has the potential for such anapplication requiring efficient heat transfer. In this work, we presentthermal contact resistance measurement results for CNT and CNT-Cu compositefilms. It is shown that Cu-filled CNT arrays enhance thermal conductancewhen compared to as-grown CNT arrays. Furthermore, the CNT-Cu compositematerial provides a mechanically robust alternative to current IC packagingtechnology.

The median-times-to-failure (t50's) for straightdual-damascene via-terminated copper interconnect structures, tested underthe same conditions, depend on whether the vias connect down to underlayingleads (metal 2, M2, or via-below structures) or connect up to overlayingleads (metal 1, M1, or via-above structures). Experimental results for avariety of line lengths, widths, and numbers of vias show higher t50's forM2 structures than for analogous M1 structures. It has been shown thatdespite this asymmetry in lifetimes, the electromigration drift velocity isthe same for these two types of structures, suggesting that fatal voidvolumes are different in these two cases. A numerical simulation tool basedon the Korhonen model has been developed and used to simulate the conditionsfor void growth and correlate fatal void sizes with lifetimes. Thesesimulations suggest that the average fatal void size for M2 structures ismore than twice the size of that of M1 structures. This result supports anearlier suggestion that preferential nucleation at the Cu/Si3N4 interface in both M1 and M2 structuresleads to different fatal void sizes, because larger voids are required tospan the line thickness in M2 structures while smaller voids below the baseof vias can cause failures in M1 structures. However, it is also found thatthe fatal void sizes corresponding to the shortest-times-to-failure (STTF's)are similar for M1 and M2, suggesting that the voids that lead to theshortest lifetimes occur at or in the vias in both cases, where a void needonly span the via to cause failure. Correlation of lifetimes and criticalvoid volumes provides a useful tool for distinguishing failuremechanisms.

The damascene fabrication method and the introduction of low-K dielectricspresent a host of reliability challenges to Cu interconnects andfundamentally change the mechanical stress state of Cu lines. In order tocapture the effect of individual process steps on the stress evolution inthe BEoL (Back End of Line), a process-oriented finite element modeling(FEM) approach was developed. In this model, the complete stress history atany step of BEoL can be simulated as a dual damascene Cu structure isfabricated. The inputs to the model include the temperature profile duringeach process step and materials constants. The modeling results are verifiedin two ways: through wafer-curvature measurement during multiple filmdeposition processes and with X-Ray diffraction to measure the mechanicalstress state of the Cu interconnect lines fabricated using 0.13um CMOStechnology. The Cu line stress evolution is simulated during the process ofmulti-step processing for a dual damascene Cu/low-K structure. It is shownthat the in-plane stress of Cu lines is nearly independent of subsequentprocesses, while the out-of-plane stress increases considerably with thesubsequent process steps.

The damage induced in the low-k material upon exposure to dry etch and ashplasmas is a point of major concern in terms of preservation of thedielectric properties. There is urgent need to assess, classify and quantifythe extent of such damage to allow the optimization of patterning processesand conditions. Meander-fork structures with spacings between 250nm and 70nmare used in this study as vehicle to compare trends in electricalperformance for different dielectrics: SiO2 and two SiOC:H low-kmaterials with pristine k values of 3.0 and 2.6. Here we demonstrate thatthe ‘electrical equivalent damage’ model is a valid and precise methodologyfor assessing dielectric damage upon processing from interline capacitanceevaluation. This analysis allows to distinguish between bulk and sidewallmodification and to quantify the extent of damage. Moreover, it provides aninterpretation for the degradation of leakage current and breakdown field ofthe interline dielectric, revealing different trends whether due to onlysidewall or total damage.

ALD WNC nucleation and growth was observed strongly affected by differentsubstrate materials and surface chemistries. Nucleation was inhibited onmost pristine low k surfaces, which is attributed to low concentrations ofchemisorption sites (Si-OH). Plasma treatments were used to alter thesurface chemistry to improve nucleation. Surface closure and surfaceroughness of the WNC layer were found to strongly correlate with startingsurface condition. Resistivities of the resulting films were also founddependent on starting surface treatment. But the relationship between Wcontent of the films, surface treatment and resistivity was not fullycomprehended.