Density functional theory was used to investigate the adsorption and reaction of HfCl4 with two hydroxyls on Si (001)-2×1 surface in atomic layer deposition (ALD) process. When H2O molecules are adsorbed on Si (001) surface at room temperature, they are dissociated with hydrogens and hydroxyls. There are two dissociation pathways; inter-dimer dissociation and intra-dimer dissociation. The activation energies of these pathways can be converted to the reaction probabilities. It was approximately 2:1. We prepared a reasonable Si substrate which consisted of six inter-dimer dissociated H2O molecules and two intra-dimer dissociated H2O molecules. The HfCl4 must react with two hydroxyls to be a bulk-like structure. There were five reaction pathways where HfCl4 could react with two hydroxyls; inter-dimer, intra-dimer, cross-dimer, inter-row, and cross-row. Inter-row, inter-dimer and intra-dimer were relatively stable among the five reaction pathways based on the energy difference. The electron densities between O and Hf in these three reactions were higher than the others and they had shorter Hf-O and O-O bond lengths than the other two reaction pathways.

Hafnium dioxide that belongs to a class of metal oxides with a high dielectric constant or high-k dielectrics has been recently introduced as a gate dielectric in field effect transistors. We report a theoretical study of structural and electronic properties of hafnia surface, and the electronic structure and band alignment at hafnia interfaces with metals, oxides and semiconductors that are crucial in gate stack engineering.

Group III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.

The growth of of metallic copper by atomic layer deposition (ALD) using copper(I) di-sec-butylacetamidinate ([Cu(sBu-amd)]2) and molecular hydrogen (H2) on SiO2/Si surfaces has been studied. The mechanisms for the initial surface reaction and chemical bonding evolutions with each ALD cycle are inferred from in situ Fourier transform infrared spectroscopy (FTIR) data. Spectroscopic evidence for Cu agglomeration on SiO2 is presented involving the intensity variations of the SiO2 LO/TO phonon modes after chemical reaction with the Cu precursor and after the H2 precursor cycle. These intensity variations are observed over the first 20 ALD cycles at 185°C.

We report on both conventional electron paramagnetic resonance (EPR) measurements of fully processed HfO2 based dielectric films on silicon and on electrically detected magnetic resonance (EDMR) measurements of fully processed HfO2 based MOSFETs. The magnetic resonance measurements indicate the presence of oxygen vacancy and oxygen interstitial defects within the HfO2 and oxygen deficient silicons in the interfacial layer. The EDMR results also indicate the generation of at least two defects when HfO2 based transistors are subjected to significant negative bias at modest temperature. Our results indicate generation of multiple interface/near interface defects, likely involving coupling with nearby hafnium atoms.

We investigate boron transient enhanced diffusion (TED) and series resistance in SiGe/Si heterojunction channel pMOSFET. The stress gradient at the SiGe/Si interface near the gate edge in high Ge concentrations are found to determine boron TED as well as extension junction shape, which has a significant impact on the parasitic LDD and source/drain (S/D) series resistance. In addition, high Ge concentrations in the epitaxial SiGe layer on top of Si substrate result in a high sheet resistance during a 1000°C/5s rapid thermal processing (RTP), which is mainly due to alloy scattering and interface roughness scattering.

As complementary metal–oxide–semiconductor (CMOS) devices are scaled down into nano-region, SiO2 dielectric is approaching its physical and electrical limits. Hafnium based oxides are the most promising materials as a replacement for conventional gate dielectrics, due to its much higher dielectric constant (high-k) and stability. The aims of work were to investigate the interface-related issues associating with Hf-based/Si and SiO2/Si gate stacks. The interfacial properties of dielectric oxide/Si were studied by stacking a different dielectric layer (SiO2, HfSiO, and HfO2) on Si substrate. We studied the electrical behavior of dielectric oxide/Si interface by leakage current density-voltage (J-V) and capacitance-voltage (C-V) measurement techniques. The effects of the post-deposition annealing (PDA) treatment on the interface charges of dielectric oxides were presented. We found that the PDA can effectively reduce trapping density and the leakage current, and eliminate hysteresis in the C–V curves. The X-ray photoelectron spectroscopy (XPS) was applied for studying the surface chemical bonding energy at different gate stack structures. The XPS analysis provides a better interpretation of the electrical property. As results, HfSiO films have exhibited a superior performance in terms of thermal stability and electrical characteristics.

Future CMOS technologies will require the use of substrate material with a very high mobility. Therefore, the combination of Ge pMOS with GaAs nMOS devices is investigated for its possible use in advanced CMOS applications. In this work, the physical, chemical and electrical properties of a-GeO2 interfacial passivation layer (IPL) for n-Ge(001) and p-GaAs(001) have been investigated, using Molecular Beam Epitaxy (MBE) technique. The efficient electrical passivation of Ge/GeO2 will be demonstrated, and in the case of GaAs, the use of a thin a-GeO2 interlayer reduces the defects at the interface.

Point Defect (PD) mediated diffusion of phosphorous in silicon is studied in order to address the long standing open problem of PD-Dopant pair lifetime. A novel experimental method is suggested to increase PD-P pair lifetime for better observability and experimental resolution. In the experiment, phosphorous is implanted, followed by low temperature poly-Si deposition with in-situ doped phosphorous. The P profile shows, after low temperature (<650°C) in-situ phosphorous doped poly-Si deposition, an exponential dependence of two orders of magnitude for a significant depth scale. This indicates that the PD-P pairs survive long-range diffusion before dissociating in the Si lattice. As a result, the lifetime of PD-P pair was extracted and this provides a physical basis for TCAD simulation at the atomic scale.

We investigated the HfO2:GaAs interface electronic structure and interface passivation by first principles calculations. The HfO2:GaAs interface of HfO2 terminated with four O atoms and GaAs terminated two Ga atoms is found to be the most energetically favorable. It is found that the interface states mainly arise from the interfacial charge mismatch, more specifically from the electron loss of interfacial As. Si or Ge as an interfacial passivating layer helps to maintain the charge of interfacial As and hence reduce the interface states.

The interface and electrical properties of HfAlO dielectric formed by atomic layer deposition (ALD) on sulfur-passivated GaAs were investigated. X-ray photoelectron spectroscopy (XPS) revealed the absence of arsenic oxides at the HfAlO/GaAs interface after dielectric growth and post-deposition annealing at 500 °C. A minimal increase in the amount of gallium oxides at the interface was detected between the as-deposited and annealed conditions highlighting the effectiveness of HfAlO in suppressing gallium oxide formation. An equivalent oxide thickness (EOT) of ∼ 2 nm has been achieved with a gate leakage current density of less than 10-4 A/cm2. These results testify a good dielectric interface with minimal interfacial oxides and open up potential for further investigation of HfAlO/GaAs gate stack properties to determine its viability for n-channel MOSFETs.

Ge monoxide [GeO(II)] and dioxide [GeO2(IV)], which are selectively formed on Ge substrate by controlling pH and redox potential in pretreatment solution, are confirmed by XPS. ΔEC in GeO(II)/Ge and GeO2(IV)/Ge are almost the same, whereas ΔEV in GeO(II)/Ge is smaller than that in GeO2(IV)/Ge, resulting in smaller Eg of GeO(II). GeO(g) desorption is suppressed in LaAlO3/Ge gate stack, whereas GeO(g) desorbs through LaAlO3 layer when there is an intentional interfacial GeO(II) layer, leading to a large increase in Jg. GeO(g) desorption temperature in Ge oxide/Ge gate stacks decreases with the increase in the ratio of GeO(II) in Ge oxide and is independent of the oxidation techniques. Since GeO(g) desorption is accompanied by H2O(g) desorption, a new model to explain the GeO(g) desorption phenomena is proposed, in which Ge(OH)2 decomposes into GeO(g) and H2O(g). Highly effective etching methods of Ge oxide, using HCl solution and HCl vapor at higher temperature than boiling point of Ge (hydro-)chloride are demonstrated.

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm CMOS technology. We present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. On Si(100), crystalline Gd2O3 grows usually as (110)-oriented domains, with two orthogonal in-plane orientations. Layers grown under best vacuum conditions often exhibit poor dielectric properties due to the formation of crystalline interfacial silicide inclusions. Additional oxygen supply during growth improves the dielectric properties significantly. Layers grown by an optimized MBE process display a sufficiently high-K value to achieve equivalent oxide thickness values < 1 nm, combined with ultra-low leakage current densities, good reliability, and high electrical breakdown voltage. A variety of MOS capacitors and field effect transistors has been fabricated based on these layers. Efficient manipulation of Si(100) 4° miscut substrate surfaces can lead to single domain epitaxial Gd2O3 layer. Such epi-Gd2O3 layers exhibited significant lower leakage currents compared to the commonly obtained epitaxial layers with two orthogonal domains. For capacitance equivalent thicknesses below 1 nm, this differences disappear, indicating that for ultrathin layers direct tunneling becomes dominating. We investigated the effect of post-growth annealings on layer properties. We showed that a standard forming gas anneal can eliminate flatband instabilities and hysteresis as well as reduce leakage currents by saturating dangling bond caused by the bonding mismatch. In addition, we investigated the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si with different orientations. The degradation of layers can be significantly reduced by sealing the layer with amorphous silicon prior to annealing.

Atomic Layer Deposition is used to deposit HfO2 and TiO2 films on GaAs (100) native oxides and etched surfaces. For the deposition of HfO2 films two different but similar ALD chemistries are used: i) tetrakis dimethyl amido hafnium (TDMAHf) and H2O at 275°C and ii) tetrakis ethylmethyl amido hafnium (TEMAHf) and H2O at 250°C. TiO2 films are deposited from tetrakis dimethyl amido titanium (TDMATi) and H2O at 200°C. Rutherford Back Scattering shows linear film growth for all processes. The film/substrate interface is examined using x-ray Photoelectron Spectroscopy and confirms the presence of an “interfacial cleaning” mechanism.

We analyze a main scheme for the suppression of GeO desorption by the high pressure oxidation which drastically improve the electrical quality of Ge/GeO2 capacitors. The inherent driving force for GeO to form at the Ge/GeO2 interface and to diffuse toward the GeO2 surface was realized by the concentration gradient in the GeO2 film, which was obtained from the thermodynamic calculation. Kinetic consideration based on the comparison with Si/SiO2 stacks suggests that GeO desorption at the GeO2 surface is the rate-limiting process under passive oxidation conditions. When O2 pressure is increased by high pressure oxidation, the vapor pressure of GeO at the GeO2 surface is reduced, restricting GeO desorption at the GeO2 surface.

We report on the growth of high-permittivity (k) TiO2 thin films on In0.53Ga0.47As channels by chemical beam deposition with titanium isopropoxide as the source. The films grew in a reaction-limited regime with smooth surfaces. High-resolution transmission electron microscopy showed an atomically abrupt interface with the In0.53Ga0.47As channel that indicated that this interface is thermally stable. Measurements of the leakage currents using metal-oxide-semiconductor capacitors with Pt top electrodes revealed asymmetric characteristics with respect to the bias polarity, suggesting an unfavorable band alignment for CMOS applications. X-ray photoelectron spectroscopy was used to determine the TiO2/In0.53Ga0.47As band offsets. A valence band offset of 2.5 ± 0.1 eV was measured.

Parasitic resistance, particularly source/drain contact resistance becomes one of the most serious problems to extend MOSFET scaling recently. Nickel silicide (NiSi), with advantages of low resistivity and high scalability, has been chosen as the material for source/drain formation. However, its Schottky barrier height (SBH) of 0.65eV for electrons is so high that it would block electrons from tunneling, therefore becomes an obstacle to further reduce the contact resistance, which is necessary to achieve the future scaling. Among several solutions, high concentration impurity-segregation layers have been introduced at NiSi/Si interfaces to reduce SBH of MS-MOSFETs. Sulfur (S) has been considered to be an efficient material for the segregation-layer to reduce SBH owing to Fermi-level pinning effect. Previous studies have investigated segregation by implanting S before NiSi formation. Because of the high diffusivity of S in Si, S profile becomes broad during silicidation process, which leads to loss of S concentration at the interface. Moreover, S ions spread into the substrate and channel region generate deep impurity levels that induce junction leakage and off leakage, resulting in device performance degradation. In this paper, S implantation after Ni silicidation is proposed to suppress S diffusion because NiSi is expected to be an efficient barrier for S diffusion. In addition, NiSi/Si interface can serve as a potential energetic valley which may trap S during thermal treatment after implantation. In this work, S was implanted into NiSi/n-Si diodes at the energy of 10keV with dose of 5�1014 and 1015 cm-3 after NiSi is formed. The projection range of S in NiSi is about 6nm, while thickness of NiSi is 16nm. Some devices were annealed at 300C and 450C. The I-V characteristics show that SBH is sufficiently reduced as the annealing temperature becomes higher, and it reaches as low as 3.4meV for 450C annealing. SBH of 3.4meV is much lower than the previously reported value of 70meV for which S was implanted before silicidation. The SIMS analysis result also proves the S profile is much sharper than having S-implantation before Ni silicidation, which supports our hypothesis that S diffusion is suppressed through our process and avoid the loss of S concentration at the interface. Moreover, despite the worry that S-implantation might damage the NiSi/Si interface morphology, cross sectional TEM images show that the interfacial flatness is completely the same as that of non-implanted NiSi/Si, indicating that no degradation occurs by S implantation. In summary, S-implantation after NiSi formation, which provides ultimately low SBH at NiSi/Si interface, is a promising technique to realize ultra-low parasitic resistance source/drain for future LSI beyond 16nm generation.

Thermal properties of five divalent ruthenium precursors with three types of structures were examined by thermal analyses. Their volatilities and the relationships between their structure and thermal stability were compared by TG analysis. Precursor volatility was found to be inversely proportional to molecular weight. The DSC result showed that substituting a linear pentadienyl ligand for a cyclopentadienyl ligand decreased the thermal stability of a precursor and precursors could be liquefied by attaching an alkyl group longer than methyl group to a Cp ligand. As a result of TG-MS analyses for Ru(DMPD)(EtCp) and Ru(EtCp)2, 2,4-dimethyl-1,3-pentadiene was found to be a thermolysis product of Ru(DMPD)(EtCp) though no thermolysis products of Ru(EtCp)2 were observed. These results show that the volatility and decomposition temperature of a divalent ruthenium precursor can be designed by adjusting the precursor's structure.

Strontium titanate (STO) thin films (45-67 % Sr) were deposited by atomic layer deposition using Sr(tBu3Cp)2/Ti(OMe)4/H2O as precursors. The Sr content of the layers is well controlled by the precursor pulse ratio, as indicated by Rutherford backscattering spectroscopy (RBS). The amount of Sr and Ti deposited depends on the Sr:Ti pulse ratio and indicates the enhancement of the Ti precursor reactivity in the presence of Sr-OH. STO compositions that are closer to stoichiometric SrTiO3 result in denser films with correspondingly higher index of refraction. The increase (decrease) of the Sr content over (below) 50 % leads to an expansion (contraction) of the lattice parameter corresponding to cubic SrTiO3 with a perovskite structure. The dielectric constant (extracted from film thickness series) and leakage current strongly depends both on the Sr content and the crystalline state of the films.

In this paper the impact of post deposition annealing in various ambient on electrical properties of hafnium zirconate (HfxZr1-xO2) high-k dielectrics is reported. ALD HfxZr1-xO2 films are annealed in a nitrogen and/or oxygen ambient at 500°C to 1000°C. Devices annealed at 500°C in N2 has lower equivalent oxide thickness (EOT) of 10Å without significant increase in gate leakage (Jg), threshold voltage (Vt) and only a slight decrease in transconductance (Gm) values compared to 500°C O2 annealed devices. Furthermore, the impact of annealing HfxZr1-xO2 films in a reducing ambient (NH3) is studied. Optimized NH3 anneal on HfxZr1-xO2 results in lower CET, improved PBTI, low sub-threshold swing values, comparable high-field Gm with only a minor degradation in peak Gm compared to control HfxZr1-xO2. Finally, the impact of laser annealing vs. RTP annealed HfxZr1-xO2 films are reported. Laser annealing helped further stabilize tetragonal phase of HfxZr1-xO2 without inducing void formation. Good devices with low leakage, low EOT and high mobility are obtained for laser annealed HfxZr1-xO2.