3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed.

In this work we propose a particle agglomeration model for chemical mechanical planarization (CMP) under the primary motivation of understanding the creation and behavior of the agglomerated slurry abrasive particles during the CMP process, which are a major cause of defectivity and poor consumable utility due to sedimentation.

The proposed model considers the slurry composition as a colloidal suspension of charged colloidal silica in an electrically neutral aqueous electrolyte. First, a theoretical relationship between the measurable chemical parameters of the slurry's aqueous electrolyte, the surface potential of the abrasive particles, and corresponding zeta potential between the agglomerated abrasive particles is presented. Secondly, this zeta potential is used in a modified DVLO interaction potential model to determine the particle interaction potentials due to both the attractive van Der Waals forces and repulsive electrostatic interactions. Finally, the total interaction potential created is then used to define a stability ratio for slow versus fast agglomeration and corresponding agglomeration rate equations between particles; these are used in a discrete population balance framework to describe the final particle size distribution with respect to time and agglomerate composition.

The proposed model will provide both a qualitative and quantitative description of agglomeration of abrasive slurry particles during CMP that can be extended to account for slurry composition or abrasive particle type, enabling more accurate process control, increased consumable utility, and possible defectivity reduction.

A model is proposed to understand the interactions between CMP pad asperities and the wafer. Pad asperity reduced modulus and height distribution are included in the model. Physical measurements of asperity properties are performed: asperity reduced modulus is measured by nanoindentation, and pad asperity height distribution is scanned by profilometry. The measured results are used in the model to predict the contact area percentage between the pad and wafer in the CMP process.

A systematic approach was taken to identify methods to prevent post CMP corrosion of copper in 22nm interconnect structures. Line to line current leakage measurements (at various times post CMP) were used as a means to quantify the extent and time-dependence of copper corrosion. Interruption of the corrosion mechanism by the use of passivating agents in post-CMP clean chemistries is explored. A broad-based screening was conducted to identify aqueous formulations of passivating agents for protection of copper which do not have deleterious effects on line resistance and overall defectivity. A formulation was identified which was effective in preventing corrosion when applied during post CMP brush clean.

The paper reports the tests results of ruthenium contacts coatings of magnetically controlled MEMS switches. During the tests the contact resistance was measured and the lifetime of MEMS switches was evaluated. After testing the analysis of the form and contact surface structure using SEM-method was carried out. The experiment results showed that the application of ruthenium nanolayers as the contact coating at slight increase of the contact resistance improves the lifetime of MEMS switches considerably.

Nowadays the increase of the lifetime of all MEMS switch types (RF MEMS relays, magnetically controlled on-off MEMS switches) is the most actual problem. The work resource and operating characteristics, first of all, contact resistance, of any switching unit, the basis of the construction of which is a dry contact, are determined by the contact coating properties. This is true for MEMS switches too.

The paper presents the results of the study of the operating characteristics of magnetically controlled MEMS switches with ruthenium and gold contact coatings of up to 100 nm thickness. During tests the following switching mode was used: switching voltage – 3 V, current - 10 μA. Each MEMS switch was subjected to 100 million cycles switching at the frequency of 100 Hz. After testing the contact surface investigation by SEM-method and electrical characteristics measurement was carried out. The paper presents SEM-images of the contacts surface and statistical date of electrical characteristics.

After 100 million switching cycles MEMS switches with nanoscale ruthenium coating have shown 100% operating capacity; 16% of switches with gold contacts turned out to be inoperative due to electrical contacts sticking.

The results of researches by SEM-method show that the contacts without nanoscale coating have the traces of strong erosion and melting; the contacts with nanoscale ruthenium coating practically did not change the form and flatness.

So, the test results indicate that nanoscale ruthenium coatings of the electrical contacts provide excellent resource for the switches operation of hundred millions and more cycles.

A yield problem is observed with tungsten vias formed on copper interconnects. Copper migration can occur during chemical vapor deposition (CVD) of tungsten, if there are defects in the liner inside the via. Copper can react quickly with SiH4 during the early stages of tungsten deposition, when SiH4-reduction of WF6 is used. Under severe conditions, large amounts of copper diffuse out of the underlying metal layer, resulting in copper silicide formation in the via and leaving voids in the copper wire. Copper migration can be minimized by reducing the time that the wafers are exposed to SiH4.

The scaling of BEOL interconnect technology in ULSI circuitry requires the integration of Cu wiring with ultra-low K (ULK) dielectrics. We present the results of a study of the interaction between different-stoichiometry Ta(N)/Cu barrier processes and porous ULK dielectrics (k=2.4) at 32nm groundrules Auger and diffraction analysis of blanket wafers was used to benchmark two different stoichiometries of TaN barrier deposited using commercially-available ionized PVD sources. Comparison TEM and EDX/EELS images indicates that barrier oxidation is occurring in the low nitrogen-content Ta(N) barrier, which is absent at the higher stoichiometry. These differences are further manifested in defect-density analysis of patterned wafers comparing the two processes. These results illustrate the critical importance the TaN barrier properties play in enabling the integration of Cu/ULK interconnects at 32nm at beyond.

The trend for future integrated circuits (IC) is decreasing in size beyond the conventional limits. The recent transition from aluminum to copper as the interconnect material for IC is due to copper's higher resistance to electromigration and its lower resistivity. Unfortunately, copper has high mobility in Si and SiO2 and may cause destruction of electrical connections on the chip. Hence, there is a significant necessity in finding ultra thin, thermally stable, high quality and good adhered diffusion barriers. The most widely used barrier is pure Ta films or layer stacks consisting of Ta and TaN. These have excellent conformality, very good uniformity and high thermal stability. But The continuous scaling down of the interconnect dimensions lead to an essential decrease in the barrier layer effective thickness to less than 5nm; coupled with the replacement of silicon oxide by advanced low-k dielectrics it demand further improvements of the diffusion barrier performance. For that reason Self-assembled monolayers (SAMs), with thicknesses of 2nm or less, have been propose for copper diffusion barrier application. By tailoring the structure of these monomolecular organic films, atomic scale properties can be controlled and selective surfaces and interfaces can be engine as desired for a specific application. In the presented work, the quality of an amino-terminated SAM barrier (NH2SAM) is tested. A high density and the absence of pinholes in the barrier layer are essential for a good barrier performance. First, the macroscopic quality of the NH2SAM barrier has been characterized by Water contact angle (CA) and High resolution AFM (HR-AFM). Secondly, the density and the presence and/or absence of pinholes have been tested by Ellipsometry and Cylic Voltametry (CV). Finally, the intrinsic barrier performance in form of Time- dependent dielectric breakdown (TDDB) lifetime has been extracted from planar capacitor structures that permitted to measure the leakage/Cu diffusion through barrier in the vertical direction. The Contact angle of layers formed at different deposition times show a variation of the hydrophilic SiO2 substrate to hydrophobic already with 1min deposited NH2SAM layer. A 15min deposited NH2SAM (~1nm), results in a continuous and pinhole free layer observed by HR-AFM. The refraction index (η) calculated by ellipsometry, indicates an increase in the density of the layer with the deposition time. On the other hand, cyclic voltametry shows inhibition of the electrochemical reduction of Fe3+ specimen to Fe2+ when NH2SAM are formed on ~2nmSiO2/Si electrodes. A decrease in the capacitive current is observed by increasing the layer thickness and density. The intrinsic barrier performance of the NH2SAM barrier by TDDB is demonstrated with an increase of 10 times the capacitor lifetime by comparing with no barrier system.

The copper precursor N,N'-diisopropylacetamidinate has been decomposed at low temperature (80-110°C) in a liquid process under a moderate H2 pressure. Depending on the choice of the solvent, the process leads to a colloidal solution of well controlled copper nanoparticles or the deposition of composite Cu-SiO2 films on the surfaces. The latter layer is highly adhesive to silica surface, behaves as an active seed layer for electroless copper deposition and allows a conformal covering inside deep trenches.

Difficulties and challenges have been widely encountered in the chemical mechanical planarization (CMP) of noble metals used as diffusion barrier films due to hardness, chemical inertness and toxic oxidation products, in particular for Ru polishing. A commercial CMC Ru polishing slurry that successfully addressed the safety concerns was based on a high pH (8.4) polymer-treated-alumina-based multi-additive slurry containing complexing reagents (carboxylic acids and salts), corrosion inhibitors, surfactants, and hydrogen peroxide as a mild, non-aggressive oxidizer. Recently, our efforts had been redirected towards the development of a new generation of low pH barrier slurries based on an entirely new concept employing unique Lewis acid type abrasives. This class of materials is well known to be highly reactive in dielectrics polishing (ceria, zirconia, titania), but far less is known about their interactions with Ru, Cu or Ta.

In this presentation, we will elaborate the unexpected discovery that hard, chemically inert, noble metals such as ruthenium can be polished easily by virtually abrasive-free and/or oxidizer-free TiO2 based slurries. Of particular importance is the finding that the polymorphic phase of TiO2 (anatase or rutile), its surface chemistry (functional groups, Lewis acid/base character), pH induced surface modification and reactivity, can all mediate the abrasive particle's adsorption properties, catalytic activity and ultimately, its slurry polishing performance.

A wide range of diamond pad conditioner (disk) designs have been characterized and key performance metrics have been collected. Relationships between design characteristics including diamond size and shape, spatial density, and tip height distribution and polishing pad wear rates and pad surface textures have been established for a variety of pads.

Estimation of the depth-of-penetration of working diamonds, from used disk analyses, allows meaningful topographic assessments of alternative conditioner designs and predictions of relative performance. An example of an improved conditioner that illustrates this design methodology is given.

Conditioner aggressiveness and its decay in various slurries have been measured to assess disk lifetime in Chemical Mechanical Planarization (CMP) processes environments. Key factors affecting disk lifetime are discussed and an improved-lifetime conditioner for use in aggressive slurries will be reviewed.

Copper-sulfide is proposed as a selective self-aligned passivation capping film on Cu lines, to improve the lines immunity against electromigration. Copper-sulfide is tenacious, having excellent adhesion (chemically bonded) to the underlying copper lines and strong adhesion to the overlying dielectric capping barrier. Contrary to other passivation schemes, Cu sulfidation is 100% selective. The sulfidation can be done by a wet or a dry process. A very thin copper-sulfide film (of about 25-100Å) will be required, and no significant increase of RC delay is expected.

The mechanism of oxide polishing at low pH in the presence of an organic cation is discussed. The role of the cation is thought to involve increasing the nucleophilicity of the silanolate active site on the particle surface by lowering the hydration state. Additionally, the activation energy of the reaction may be lowered by charge attraction between the particle and wafer surface and by increased hydrophobic interactions.

We have developed a novel surface treatment process using vacuum ultraviolet (VUV) light with a wavelength of 172 nm and formic acid vapor. A previous study showed that the VUV process can help remove the organic contaminants on the bonding surfaces and improve the shear strength. This new work focuses on studying the effects of VUV/O3 and formic acid treatments. The formic acid (HCOOH) vapor removes the metal oxides from the surfaces before the bonding process. Evaporated Cu/Sn and immersion Au were used for the bonding micro-bumps and bonding pads in our evaluations. Different cleaning conditions with VUV/O3, formic acid vapor, or both were compared and evaluated. X-ray Photoelectron Spectroscopy (XPS) was used to study the surface elemental composition of the micro-bumps and pad surfaces before and after the cleaning process. The photoelectron spectra of C1s, Sn3d, and Au4f were obtained with XPS. The XPS results showed the atomic carbon concentrations were significantly decreased by the VUV/O3 treatment process, while the Sn and Au concentrations were increased by the VUV/O3 and formic acid treatment because of the removal of the organic contaminants and metal oxides from the surfaces. The bonding strength of the Cu/Sn bumps was evaluated using a shear test tool. The results shows that the combination of VUV/O3 and formic acid treatment obtains the highest average shear strength among the treatments tested, with a shear strength almost 2.5 times stronger than the untreated samples.

Through-silicon via (TSV) structures with various material and geometry configurations are assessed to study their impact on reliability, isolation and performance. Oxide liner insulators show a larger performance impact as compared to low-k liners and the effect decreases with increasing liner insulator thickness. Higher density of the TSV array causes greater stress impact on carrier mobility and increases the parasitic capacitance. Additionally, low-k liner reduces the parasitic capacitance, but exhibits lower strength and adhesion, therefore degraded reliability. These results provide an important perspective of performance and reliability trade-offs necessary for a robust TSV design.

Optimisation of spatial uniformity of material removal in chemical mechanical planarization requires an understanding of the mechanics of the wafer carrier system. Finite element analyses have been carried out by researchers identifying relationships between von Mises stress distribution and material removal rate. However, in many of these wafer scale models, the derivation of the material properties of the polishing pad and sub pad is unclear and consequently a large variation in values used is observed. Models are generally validated with a procedure different to that simulated in the model and with different output variables. Few models have incorporated the industry standard method of pressurizing the backside of the wafer independently to the wafer carrier loading using a pressurized air chamber located directly behind the backside of the wafer. The anticipated introduction of 450mm diameter wafers has surprisingly not been accompanied by wafer scale models investigating the issues that will arise from the diameter and thickness scaling ratio of the wafer.

This paper presents a unique approach to finite element modeling of CMP incorporating realistic boundary conditions for the wafer carrier and platen assemblies. Model predictions of interfacial contact pressure for a 200mm wafer loaded by a lip seal type carrier head were validated by unique measurements of the contact pressure between the wafer and the pad using Fujifilm Prescale TM pressure measurement film and accompanying analysis software. The results demonstrated a close correlation between the model's prediction and the measured values. Results are presented for the upscaling of this validated model to 450mm wafer dimensions. The results indicate a doubling of the contact pressure maximum values compared to the 200mm wafer model. These results illustrate the extent of the challenge facing CMP tool vendors in increasing the level of control of the mechanical force distributed by the wafer carrier on 450mm wafers. The model can be used as a design tool to optimize machine and process parameters.

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.

Low temperature bonding is desired for compatibility with back-end-of-line processing (BEOL) conditions in order not to affect the three dimensional (3D) Integrated Circuits (IC) device performance. In this paper, the aim is to demonstrate that thermocompression bonding temperature can be lowered by changing the copper (Cu) film with Cu nanowires fabricated via electrodeposition through anodized aluminum oxide (AAO) template. A comparison was done between film-to-film (Film-Film) and nanowires-to-nanowires (NWs-NWs) bonding in terms of microstructure and shear strength. Cross-sectional images captured by Focused Ion Beam (FIB) revealed good interface between NWs-NWs bonding as the nanowires had fused together. Scanning Electron Microscope (SEM) images of samples after shear test also demonstrated that there is good adhesion between the bonding layers. Results from shear tests showed an increase in shear strength of NWs-NWs bonding as compared to that of Film-Film bonding at 200 °C. In addition, NWs-NWs bonding at 300 °C achieved higher shear strength than at 200 °C. In this study, it has been shown that copper nanowires fabricated via electrodeposition through porous AAO template can be a potential method to form a bonding intermediate layer for 3D ICs.

Through-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for metals CMP applications. For front-side TSV polishing, challenges include the removal of large amounts of copper overburden, dishing control during copper clearing steps, and removal of large amounts of barrier metal and dielectric layers while still maintaining control over topography and defectivity. Additionally, the choice of barrier material can have significant impact on polishing in terms of the mechanical reliability regarding adhesion between the barrier metal and underlying dielectric layers. This paper will address many of these challenges with an emphasis on innovative technologies for superior process and endpoint controls, such as real-time profile control for thick copper films up to 6μm or more in thickness and automatic endpoint controls for barrier removal and dielectric stopping. The paper will also discuss some salient challenges for back-side TSV polishing, including the handling and polishing of bonded wafer pairs and strategies to minimize handling and polishing damage to the potentially fragile thinned device wafer. Additionally, the development of slurries with highly tunable copper-to-dielectric selectivity will be critical for enabling a wide range of final topographies, depending on requirements for subsequent bonding steps.

Microelectromechanical Systems (MEMS) market is a rapidly growing market with a wide range of devices. Most of these devices require an interaction with an electronic circuit, and with the increasing number of high performance MEMS devices that are being introduced, a demand for integrating CMOS and MEMS using high-density and low-parasitic interconnects have also been on the rise.

Unfortunately, conventional methods of integrating CMOS with MEMS cannot provide the high density and low-parasitic interconnections required by modern high performance MEMS devices, and at the same time provide the flexibility required to accommodate new devices that are made using new materials and highly innovative fabrication processes.

Heterogeneous 3D integration of MEMS and CMOS has the potential to provide both the performance and the integration flexibility; however there are two interconnect challenges that need to be addressed. This paper outlines the details of these interconnect challenges and introduces two interconnect technologies, Mechanically Flexible Interconnects (MFI) and Through-Silicon Via (TSV), developed specifically to address these challenges.