Materials and electrical properties of the MOS capacitor containing nc-RuO embedded in the high-k ZrHfO dielectric film have been studied. The electron- and hole-trapping capacities and trapping sites in this kind of device were investigated using the constant voltage stress method, the frequency-dependent C-V measurement, and the retention characteristics. The negligible charge trapping phenomenon in the non-embedded device rules out the possibility of any trapping site in the bulk ZrHfO film or at the Si/ZrHfO interface. The electrical characterization result suggests that electrons are trapped in the bulk nc-RuO. However, holes have two possible trapping sites, i.e., in the bulk nc-RuO or at the nc-RuO/ZrHfO interface.

In this paper, the fabrication of Ge-NCs embedded in Al2O3 and HfO2 layers by ion-beam-synthesis for memory applications is investigated. Structural properties of the high-k layers before and after implantation and annealing were studied by TEM observation and EELs analysis. Spherical Ge-NCs 5nm in diameter were observed in Al2O3 implanted layers after furnace annealing at 800°C in nitrogen. Annealing studies in the range 700-1050°C in nitrogen revealed the evolution of the charge storage properties of these structures utilizing MIS capacitors test structures. No NCs were observed in HfO2 implanted layers. However, significant negative-differential-resistance regions were observed in I-V characteristics of the related MIS structures. These may be attributed to the formation of conductive paths made of hafnium germanide (HfGe2) or hafnium germanate (HfGeO) regions.

Tungsten (W)-substituted SBT ceramics [SrBi2(Ta1-xWx)2O9; 0.0 ≤ x ≤ 0.20] were synthesized by solid state reaction method using different sintering temperatures (1100 οC, 1150 οC, 1200 οC and 1250 οC). W substitution is found to significantly affect the electrical properties of SBT, including dielectric permittivity, Curie temperature, and ferroelectricity. Dielectric constant (εr) and the Curie temperature (Tc) increase with increasing W content. The dielectric loss reduces significantly with increase in W concentration. The maximum Tc of ~ 390 οC is observed in the sample with x = 0.20 as compared to ~ 320 οC for the pure sample when sintered at 1200 οC. The peak ε increases from ~ 270 in the sample with x = 0.0 to ~ 700 for the composition with x = 0.20, when sintered at 1200 οC. All the tungsten-substituted ceramics have higher 2Pr than that in the pristine sample. The maximum 2Pr (~25 μC/cm2) is obtained in composition with x = 0.05 sintered at 1200 οC. These effects have been interpreted based on the model of the recovery of oxygen vacancies upon W substitution. Such compositions with low loss and high Pr values should be excellent materials for highly stable ferroelectric memory devices.

An in-depth study of the structural and electrical properties of silicon (Si) films deposited by a novel low temperature technique at temperatures less than 400°C in a 13.56 MHz RF PECVD reactor is reported. The method is based on substrates having to undergo some initial preparatory steps (IPS) before the deposition of Si films in the PECVD chamber. The optical band gap of Si films deposited using this novel technique narrowed to 1.25 eV from 1.78 eV using the traditional a-Si:H deposition recipe. No annealing of any form was performed on the films to attain this band gap. Furthermore, photosensitivities for these films under various deposition conditions were of order 100 compared to 104 for a-Si:H films deposited under like conditions. Using metal-insulator-semiconductor devices, the Si films grown by this novel technique exhibit charge storage and memory behaviour unlike their amorphous counterparts. However, device endurance has been found to be inadequate, probably due to the presence of some contaminants - notably interstitial oxygen - which has been found elsewhere to have adverse effects on the electrical characteristics of Si films. If well harnessed, we suggest Si structures grown by this novel growth technique could be well-suited for flash memory applications, particularly 3-D flash which requires process temperatures to be less than 400 °C.

The forming voltage and set/reset response of sputter-deposited NiO thin films is studied as a function of implant fluence for samples implanted with Ni and O ions. The forming voltage of the films is shown to decrease with increasing ion fluence and to scale with the damage production rate of the different ions. In contrast, the set/reset response of the films was largely unaffected by the ion-implantation. These results are discussed in terms of the filamentary model of conduction and the thermochemical model of resistive switching.

Thin films of magnetite (Fe3O4) are grown on a single-crystal Si/SiO2 (100) substrate with native oxide using DC reactive sputtering technique at room tempreture (RT) and 300C. The x-ray diffraction(XRD) result shows the thermal energy during deposition enhances the crystallization of the Fe3O4 and x-ray photoelectron spectroscopy confirms the film deposited at 300C is single-phase Fe3O4 while the film deposited at RT is mostly ν-Fe2O3. The electrical measurements show that the resistivity of the Fe3O4 film increases exponentially with decreasing temperature, and exhibit a sharp metal-insulator transition at around 100 K, indicating the Verwey transition feature. The saturation magnetization Ms of Fe3O4 film measured by vibrating sample measurement (VSM) at RT was found to be 445 emu/cm3.

Although conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the > 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.

Low temperature (400°C) deposition of ferromagnetic Ni-Mn-Ga thin films is successfully performed via rf magnetron sputtering technique using co-deposition of two targets Ni50Mn50 and Ni50Ga50 on sapphire (0001) and Si (100) substrates. The films are in part amorphous with significant degree of crystallinity. The obtained crystallographic structure is shown to be substrate-dependent. Films on both substrates are ferromagnetic at room temperature (Curie temperature ∼ 332.5K) with well-defined hysteresis loops, low coercivity (∼ 100 Oe) and a saturation magnetization of ∼ 200 emu/cc. At low temperature (5 K), both films show increased magnetization value with wider hysteresis loops having higher coercivity and remanent magnetization. The process is therefore effective in achieving the appropriate thermodynamic conditions to deposit thin films of the Ni-Mn-Ga austenitic phase (highly magnetic at room temperature) at relatively low substrate temperature without the need for post-deposition annealing or further thermal treatment, which is prerequisite for the device fabrication.

In this paper, fabrication of nanocomposite thin films with introduction of fullerene (C60) molecules in PolyMethyl MethAcrylate resist (PMMA) was investigated from a material and electrical point of view. The effective inclusion of C60 molecules in the samples was characterized by using UV-vis and Tof-SIMS instruments. The modified resist PMMA:C60 was also studied with Thermal analysis (TGA, DSC) where modification of physical properties is reported. Films were included in MIS and MIM devices and results on non volatile trapping of C60 doped PMMA are presented. Moreover, e-beam exposure tests showed that PMMA:C60 active layers for memory devices, were scalable in size.

Doped SbTe phase change (PRAM) line cells produced by e-beam lithography were cycled for at least 100 million times. The memory retention of the PRAM cell was measured both isothermally and isochronally which showed excellent agreement. An activation energy for growth of 1.7 eV was found (after 100 million cycles) for both measurements. Similar isothermal and isochronal measurements were performed on PRAM cells produced by optical lithography which yielded activation energies of 3.0 eV and 3.3 eV, respectively. Our results show that the same phase-change material can show large differences in retention behavior depending on the way the cells are produced.

AgInSbTe (AIST)-SiO2 nanocomposite layer prepared by a one-step sputtering process utilizing target-attachment method was implanted in the nonvolatile floating gate memory (NFGM) devices. Device sample subjected to post annealing at 400°C for 2 min in atmospheric ambient exhibited a significant hysteresis memory window (ΔVFB) shift = 5.91V and charge density = 5.22×12 cm-2 after ±8V voltage sweep. During the retention time test, a ΔVFB shift about 3.50 V and charge loss about 28.4% were observed in the sample after a ±5V voltage stress for 104 sec. Cross-sectional TEM revealed that the nanocomposite layer contains the crystalline AIST nanoparticles with the sizes about 5 to 7 nm embedded in SiO2 matrix. XPS analysis indicated that annealing induces the reduction of antimony oxides to form metallic Sb nanocrystals and suppresses the oxygen defects and charge loss in nanocomposite layer. Analytical results illustrated that the utilization of AIST-SiO2 nanocomposite layer may simplify the preparation of NFGM device with satisfactory electrical properties, implying a promising feasibility of such a nanocomposite layer to NFGM devices.

The systematic investigation on the thermal stability of the CoO layer was carried out for various electrode materials. When Pt with higher oxygen potential (Gibbs free energy change of the oxidation reaction) compared to Co is used as electrodes, the resistance of the Pt/CoO/Pt devise was severely decreased by the post deposition annealing (PDA) process and the resistance switching into the high resistance state was observed in the first voltage sweep. This indicants that the reducing Ar ambient induces the quite local reduction of CoO. The reduction of the CoO layer is also expected even with the Co electrode, which is reasonably attributed to the oxygen concentration gradient at the Co/CoO interface in the Co/CoO/Pt device. With the Ti electrode having a much lower oxygen potential than Co, the reduction of CoO by Ti is also indicated electrically in the Pt/CoO/Ti device. On the other hands, W electrodes which is thought to have the solid-solution oxygen can stabilize the CoO layer during PDA although W is more affinitive with oxygen compared with Co. It can be pointed out the oxygen delivery at the electrode/oxide layer interface is a critical factor in designing the thermally stable stacking structure for resistance random access memory.

A chain FeRAMTM is the best solution to realize high-speed and high-bandwidth nonvolatile RAM with low power dissipation. In this paper, the overview of chain FeRAM, the technical trend for FeRAM scaling and the marketing strategy are presented. First of all, the concept and performance of chain FeRAM are described. Secondly, the status and history of chain FeRAM development are presented. Thirdly, four kinds of scaling strategies for chain FeRAM are presented; (1) A shrink trend of chain cell including a capacitor plug shared with twin cells, and process techniques including Ir/TiAlN-barrier metal and MOCVD-PZT with SrRuO3 electrode, which are installed in 16Kb, 8Mb, 32Mb, 64Mb and 128Mb chain FeRAMs, (2) Capacitor damage suppression processes to reinforce step coverage and protect H2 damage even in 0.1μm2 capacitor of 128Mb, (3) A scalable array architecture such as an octal / quad bitline architecture to reduce bitline capacitance and ensure enough cell signal in scaled ferroelectric capacitor, and (4) A ferroelectric capacitor overdrive technique by driving shield-bitlines to enlarge tail-to-tail cell signal in low voltage operation of 1.3V. Fourthly, future direction of chain FeRAM is discussed. The vertical capacitor is one of candidates for gigabit-scale chain FeRAMs, and solves signal problem and achieves small 4F2 cell without contact formation. Finally, the marketing strategy to take full advantage of chain FeRAM is presented. A nonvolatile FeRAM cache is the promising candidate to achieve high bandwidth memory systems. Applications of chain FeRAM to solid-state drive (SSD) and hard-disk drive (HDD) and their system performance improvements are demonstrated.

We report resistive switching characteristics in Pt/ZnO/Pt devices where ZnO thin film is fabricated at various oxygen conditions. With the increase of oxygen contents in ZnO thin film, the forming voltage is gradually increased while reset and set voltages are almost unchanged. We also investigated the effect of top electrodes on resistive switching of top electrode/ZnO/Pt device. For a Pt/ZnO/Pt device, it exhibits the excellent resistive switching behavior due to high electrical field of the well-defined Schottky barrier. For Al/ZnO/Pt device, little resistive switching phenomena were occurred due to leakage current of the weak Schottky (or Ohmic) contact.

A direct synthesis of (001) oriented nanostructured CoPt thin films has been successfully achieved using a 880 J pulsed Dense Plasma Focus (DPF) device operating in a non-optimized focus mode with a low charging voltage of about 8 kV. The (001) oriented fct structured L10 phase nanostructured CoPt thin films have been synthesized directly in as-deposited sample, as verified by XRD results, without any post deposition annealing. The SEM imaging results show that nanostructured CoPt were achieved in non-optimized focus mode with agglomerate/particle size ranging from 10 to 55 nm. Furthermore, the VSM analysis shows that the as-deposited samples in non-optimized focus mode have higher coercivity (due to direct L10 phase) as compared the annealed sample and the as-deposited sample of optimized focus mode operation.

In this paper, we present CVD (Chemical Vapor Deposition) growth and passivation of tungsten (W) and titanium nitride (TiN) nanocrystals (NCs) on silicon dioxide and silicon nitride for use as charge trapping layer in floating gate memory devices. NCs are deposited in an 8 inches industrial CVD Centura tool. W and TiN are chosen for being compatible with MOSFET memory fabrication process. For protecting NCs from oxidation, a silicon shell is selectively deposited on them. Moreover, for a better passivation, TiN NCs are encapsulated in silicon nitride (Si3N4) in order to get rid of oxidation issues. After high temperature annealing (1050°C under N2 during 1 minute) XPS measurements point out that NCs are still metallic, which makes them good candidates for being used as charge trapping layer in floating gate memories.