Solid phase doping from Sb heavily-doped Si films has been studied by using transmission electron microscopy and secondary ion mass spectroscopy. Based on the results of the material study, metal-oxidesemiconductor field effect transistors (MOSFETs) made on a (100) Si wafer, and thin film transistors have been implemented. The technique for the MOSFETs suggests the possibility for making small dimensional and high speed integrated circuits by using the method of solid phase doping.

Highly conductive p+-polysilicon films were fabricated over Si(100) and SiO2 surfaces using high-dose ion implantation and rapid thermal annealing. Resistivities close to that of single crystal silicon were achieved. These films were characterized by a variety of electrical and optical techniques as well as SIMS and cross-section TEM.

This paper discusses the diffusion behavior of P, B and As from as-deposited amorphous/ polycrystalline silicon into the underlying Si substrate as a function of RTA/ furnace annealing conditions. The evolution of grain microstructure has been studied in as-deposited amorphous/ polycrystalline silicon to determine the inter-dependency of diffusion behavior and grain microstructure. After 60 s RTA at 1100° C for P doping, the microstructure of asdeposited amorphous silicon is drastically changed by rapid grain growth, whereas it is only slightly changed for asdeposited polysilicon. This leads to formation of deeper junctions for as-deposited polysilicon than for as-deposited amorphous Si. For B doping, there is little difference in the final microstructure between as-deposited polysilicon and as-deposited amorphous silicon after anneal. For low annealing temperatures, the junctions for both amorphous and polysilicon diffusion sources are laterally uniform in spite of local inhomogeneities due to grain boundaries. This is believed to be due to the rapid lateral spread of dopants along the interface prior to indiffusion into the substrate. At high annealing temperatures, a number of dark fringes are observed in the substrate along the interface from Crosssectional Transmission Electron Microscopy (XTEM) micrographs, which are more conspicuous for as-deposited amorphous Si. We believe that these fringes arise from local doping inhomogeneities or lattice strain in the substrate. For 30 s RTA at 1150° C, the native interfacial oxide appears to break up, causing epitaxial alignment of the polysilicon layer with respect to the underlying substrate.

In a search for low-cost and high efficiency solar cell manufacturing, several techniques of growing thin silicon sheets from powder have been adopted, such as: plasma spraying on various substrates, zone-melting using incoherent focussed light as heat source, and low-angle horizontal pulling of thin ribbon over the melted tin-lead support. Undoped, and n- and p-type silicon powders of various grain sizes have been used as starting materials, with pure graphite, quartz, or low-cost ceramics serving as temporary or permanent substrates. N+/p +/n junctions, and back surface fields were formed by implanting PF 5 and BF 3+ ions in a glow discharge ion implanter at ultralow energies (less than 1 keg) and high total ion doses. Ion induced damage was annealed by RTP in the incoherent light furnace at temperatures as low as 700°C.

Structural and optoelectronic properties of as-grown and processed thin polysilicon sheets were determined by Raman spectroscopy, spectral response, and electrical transport measurements. A sharp peak at 520 cm−1 in the Raman spectra, associated with TO ((Г) phonons, indicated a good crystallinity of polysilicon sheets. High values of short-circuit currents, and an almost flat spectral response down to 400 nm, without intentionally applying a surface passivating oxide, illustrate the advantage of the applied novel technologies.

Abstract; Grain boundary (GB) recombination is a controlling factor in the electronic properties of polycrystalline silicon. We would like to report computer modeling of the variation of electron transport parameters with depth, under illumination. The GB barrier height (Vg) versus photogeneration rate G and depth are presented, along with the resulting electron lifetime (π), mobility (µ) and diffusion length (L). Under AM1 illumination, Vg increases whereas -π, µ and L all decrease drastically with increasing depth. The GB trap density is used as a parameter, and strongly influences transport parameters in both dark and light cases.

In silicon bicrystals grain boundaries (GBs) become recombining after they have been annealed in argon at temperatures higher than 800°C for tens of hours. In order to verify the eventual influence of metallic elements, interstitials gold atoms are introduced in the bicrystals by diffusion (T ≤ 8000 C) from gold dots deposited far from the GB (gold could be segregated by the GB but cannot give deep levels in the grains). It is found by DLTS, EBIC contrast and LBIC scan map that the recombination strength of GBs is not changed by gold in diffusion in as grown bicrystals, while it is reduced in annealed samples. Similar results are obtained with GBs of polycrystalline wafers.

It is concluded that the activation of GBs in CZ silicon bicrystals is certainly due to the segregation of a slow diffuser like oxygen, and that fast diffusers play a secondary role only.

The conductivity of single grain boundaries of electronic grade, Bridgman grown polycrystalline silicon samples was measured using the dc polarization technique with the aim of detecting any influence on the carrier transport regime resulting from the segregation of oxygen and carbon, which, by themselves, should behave as electrically inactive impurities. To this scope as grown samples and samples heat treated at 1123 and 1223 K, differing in their initial oxygen and carbon content, were used and the conductivity measured in the 298-100 K range.

The results indicate that for both the carbon rich and for the oxygen rich samples the conductivity across the grain boundaries is of the thermally activated type and that it could be discussed in terms of carriers which are thermally emitted over the barrier and cross the barrier in the limit of the short mean free path.

Samples which do not present a net excess of oxygen or carbon, apparently behave as single crystal specimens, instead.

The deconvolution of the I-V curves is then used for obtaining the densitl of the interface states responsible of the set-up of the grain boundaries barrier, whose shape supports a completely new hypothesis about the configuration of the impurity cloud at the grain boundaries.

This article describes the application of in situ, high-resolution electron microscopy to the study of crystal nucleation and growth in amorphous silicon. It is shown that dynamic events at elevated temperatures (e.g. 600-750°C) can be recorded at the atomic level by such an approach. It is anticipated that fundamental information, important for the technological development of polysilicon thin films, can be generated by work of this type.

This paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

Undoped LPCVD polysilicon films deposited on thermal oxide and prepared under various process conditions have been investigated for their texture and stress characteristics. Pole figures measured by X-ray diffraction in reflection geometry were used to determine the orientation. distribution function which provides a quantitative description of the texture. Stresses were determined using wafer curvature measurements. Both texture and stress show substantial variation with deposition condition. Textures typically exhibit axial symmetry and appear to be correlated with the sign and magnitude of the stress. Under certain deposition conditions, the stress varies considerably along the tube, with the stress in the wafers at the upstream end being tensile and at the downstream end being compressive.

Reduced stress silicon nitride and undoped, as deposited, polysilicon films have been characterized on a variety of silicon based substrates within the confines of co-fabrication compatibility of micromechanical structures with VLSI processing. Average stress and stress uniformity through the films are shown to vary with substrate parameters.

Photoluminescence (PL) measurements have been carried out in hydrogenated and as deposited polycrystalline silicon thin films deposited on quartz substrates. Behavior of the PL spectrum as a function of temperature and intensity in the hydrogenated samples is reported. A mechanism that provides a qualitative explanation for the observed PL results is described. In the unhydrogenated sample the signal was much weaker and we were unable to observe any signals over an appreciable range of intensity and temperatures. The cause for much lower signals in the unhydrogenated sample is most likely due to higher surface recombination velocity.

Variable angle spectroscopic ellipsometry was used to characterize polysilicon multilayer structures. Five different multilayer wafers, each containing a polysilicon layer, were studied. Layer thicknesses and compositions were determined at several locations across each wafer. The thickness measurements obtained by ellipsometry are compared with those determined from cross-sectional transmission electron microscopy (XTEM).

The electrical properties have been investigated on boron-doped polycrystalline silicon films with the average grain size of 50 nm and of 370 nm. It is shown that Hall mobility is strongly dependent on the grain size, and the temperature dependence is changed by hydrogenplasma treatment (HPT).

After the treatment in the larger grain film, the mobility of about 40 cm2/V sec is obtained and it shows the boron acceptor level of 0.043 eV, which is almost the same as that of the level in monocrystalline silicon. A kink in the mobility vs temperature curve which is observed in the smaller grain film disappears by HPT.

These phenomena will be discussed in relation to the density of the trapping states at the grain boundary of the films.

Polycrystalline silicon has found numerous applications in silicon integrated circuits, initially as a MOS gate material, and later for advanced isolation, capacitor electrodes, resistors, interconnect, bipolar emitters and bases, trench refill, doping sources, and the active material in thin film transistors. Integration of these techniques in a BiCMOS technology requires knowledge of the interactions between the processing steps, and their cumulative effect on the final device and circuit operation. New process techniques also present opportunities for process simplification, added functionality, or improved performance. Examples of polysilicon applications that interact with other process steps and influence device performance are P+ and N+ poly gates and silicidation of gate poly. Silicidation improves circuit speed and provides additional integration opportunities in the form of faster local interconnect, but it may create a problem for older designs with synchronous timing circuitry. More innovative integration of polysilicon includes improved deposition techniques, such as the use of amorphous silicon, “Lo-Hi” poly, in sinat doping, and deposition from disilane sources enable more flexible process design. Other innovations include polysilicon emitters, bases, and buried sinkers in bipolar design, polysilicon sidewall spacers in CMOS, and polysilicon based active transistors for display applications and three dimensional integration.

In 1982, Kurt Petersen published “Silicon as a Mechanical Material” in the Proceedings of the IEEE. This thorough review article heightened focus on the advantages of utilizing the mechanical as well as electrical properties of single-crystal silicon. Processes for shaping single-crystal silicon based upon selective etching were shown in the article to make silicon useful for a variety of miniature mechanical devices.

The progress in IC technology is unthinkable without the extensive use of polysilicon for a wide variety of purposes. These range from simple passive components like resistors and contacts through more complex structures such as recrystallized layers for SOI and 3D techniques, poly-Si filled isolation trenches and electrodes of DRAM capacitors to active device applications, i.e. MOS gates and poly-Si emitters in bipolar transistors. As silicide or in combination with such polysilicon allows practical local interconnects.

Polysilicon is a key material widely used in MOSFET, bipolar, and BICMOS devices. As these technologies evolve into the deep submicron regime, several issues emerge in the applications of polysilicon that must be addressed. In sub-0.5µm MOSFET, fabrication and reliability of n + poly for NMOS and p + poly for PMOS should be studied. In bipolar technology, scaling limits of polysilicon emitter must be investigated. Understanding polysilicon, both in terms of its basic material and process characteristics and its characteristics in specific integrated process and/or integrated device structures, is definitely required in order to realize the full potential of ULSI technologies.

In EEPROMs mèmory devices, tunnel oxides with high fluence, and interpoly oxides with low conductivity and high breakdown field are needed. Tunnel oxide fluence is degraded by high temperature annealing after the polysilicon deposition, while interpoly oxide is degraded by low temperature oxidation, particularly on rough films. As a consequence, a process optimization, giving a good compromise between these two quantities is required. In this work we shown that if a flat polysilicon is used, an interpoly oxide of good quality can be obtained at low temperature, maintaining a high value for the tunnel oxide fluence.

Experimental results on the influence of prooessing on degradation of thin silicon dioxide films are reported. The high temperature polysilicon oxidation degrades the integrity and robustness of thermally grown dry oxide as shown by constant current charge to breakdown measuremeits.

Furthermore the influence of high temperature processing on the charge trapping properties of the tunnel oxide (silicon dioxide) are ascertained. The details of electron trapping its capture cross section, areal concentration and trapping efficiency as studied by high field dark current-voltage method is presented. Generally, the dominant −15 electron trap with a large capture cross section of 10 cm2 is observed and is believed to be due to phosphorus near polysilicon/thin oxide interface. In addition the QBD reduction is correlated to outdiffusion of water from the thin oxide as seen by reduction in the hysteretic instability of I-V curves.