A new deep level transient spectroscopy (DLTS) technique is described, called half-width at variable intensity analysis. This method utilizes the width and normalized intensity of a DLTS signal to determine the activation energy and capture cross section of the trap that generated the signal via a variable, kO. This constant relates the carrier emission rates giving rise to the differential capacitance signal associated with a given trap at two different temperatures: the temperature at which the maximum differential capacitance is detected, and an arbitrary temperature at which some nonzero differential capacitance signal is detected. The extracted activation energy of the detected trap center is used along with the position of the peak maximum to extract the capture cross section of the trap center.

The influence of deep level defects lateral distribution in active layers of multicrystalline Si-based standard solar cells is investigated. Multicrystalline p-type Si wafers with 156×156 mm dimensions and 200 μm thickness were used for SCs preparation. One type of solar cells with conversion efficiency 20.4% was studied using capacitance voltage characteristics method (C-V) and by current deep level transient spectroscopy (I-DLTS). From various places along the diagonal of solar cell’s substrate with 20.4% efficiency nine pieces with an area ∼20 mm2 were extracted and studied. I-DLTS spectra of the five pieces from solar cell were measured. The features of deep levels defects concentration lateral distribution along the SC’s surface were studied.

This paper presents a detailed trap investigation based on combined pulsed I/V measurements, drain current transient (DCT) measurements and low-frequency dispersion measurements of transconductance (LF Y21) and output conductance (LF Y22). DCT characterization is carried out over a 7-decade time scale. LF Y21 and Y22 measurements are carried out over the frequency range from 100 Hz to 1 GHz. These combined measurements were performed at several temperatures for AlGaN/GaN high electron mobility transistors under class AB bias condition and allowed the extraction of the activation energy (Ea) and the capture cross section (σc) of the identified traps. Extensive measurements of these characteristics as a function of device bias are reported in this work to understand the dynamic trap behavior. This paper demonstrated a correlation between LF small-signal (LF Y21 and Y22) and large-signal voltage steps (DCT) results. These measurements allow identifying the same 0.64 eV deep level, attributed to a native defect of GaN, possibly located in the buffer layer.

The influence of deep level defects (DLs) on the conversion efficiency of multicrystalline Si-based standard solar cells (SCs) is investigated. Multicrystalline p-type Si wafers with 156×156 mm dimensions and 200 μm thickness were used for SCs preparation. Three types of SCs with conversion efficiency 10%, 16.8% and 20.4% were studied using capacitance voltage characteristics method (C-V) and by current deep level transient spectroscopy (I-DLTS). The correlation between the total concentration of DLs and the values of the SCs conversion efficiency is found.

Aluminum doped ZnO (AZO) has been deposited on (100), (110) and (111) oriented n-type Si and on fused silica by atomic layer deposition (ALD). The films have been post deposition annealed in the temperature range 200-500 οC. The AZO films have been characterized by X-ray diffraction (XRD), Hall and transmittance measurements. Circular diodes have been fabricated from the AZO/Si structures and characterized by current-voltage (IV) and deep level transient spectroscopy (DLTS). The AZO films form Schottky junctions with the Si substrates for all the crystallographic orientations. It is established that after post deposition annealing the structure AZO/n-Si (110) is distinguished as the system with largest rectification.

We have investigated the electrical properties of a ZnO microwire grown by carbo-thermal evaporation, a ZnO thin film grown by pulsed-laser deposition on an a-plane sapphire, and a hydrothermally grown Zn-face ZnO single crystal (Tokyo Denpa Co. Ltd.). The samples were investigated by means of current-voltage measurements, capacitance-voltage measurements, and deep-level transient spectroscopy.

The defects T2 [1,2] and E3 [1,3,4] were identified in all three sample types. Additionally, in the single crystal and thin film samples E64 [5] and E4 [1] were detected. These findings support the common opinion that T2 is an intrinsic defect since it is found in all the samples investigated and thus its occurrence is not related to any growth technique.

High electron mobility transistors (HEMTs) based on AlGaN/GaN hetero-structures are promising for both commercial and military applications that require high power, high voltage, and high temperature operation. Reliability and radiation effects of AlGaN-GaN HEMTs need to be thoroughly studied before they are successfully deployed in potential satellite systems. A few AlGaN HEMT manufacturers have recently reported encouraging reliability, but long-term reliability of these devices under high electric field operation and extreme space environments still remains a major concern. A large number of traps and defects are present in the bulk as well as at the surface, leading to undesirable characteristics including current collapse. The present study is part of our investigation to study traps and defects in the AlGaN HEMT devices using micro-analytical techniques before and after they are life-tested.

We report on electrical properties in [(Ge+SiO2)/SiO2]×2 films deposited by magnetron sputtering on a periodically corrugated-rippled substrate and annealed in vacuum and forming gas. The rippled substrate caused a self-ordered growth of Ge quantum dots, while annealing in different environments enabled us to separate charge trapping in quantum dots from the trapping at the dot-matrix and matrix-substrate interfaces. We show that the charge trapping occurs mainly in Ge quantum dots in the films annealed in the forming gas, while Si–SiO2 interface trapping is dominant for the vacuum annealed films.

An effect of electron irradiation on the concentrations of deep-level centers in C-rich and Si-rich 6H-SiC wafers is investigated. In the former material, the main deep-level centers with activation energies of Ec-0.50, Ec-0.64 and Ec-0.67 eV are found to be related to dicarbon interstitials and CiNC complexes located in hexagonal and quasi-cubic lattice sites, respectively. In the latter material, the dicarbon interstitials are dominant after the irradiation with 1.5-MeV electrons. At the energy of bombarding electrons equal to 0.3 and 0.7 MeV, the activation energies of the dominant deep-level centers are Ec-0.38 and Ec-0.52 eV, respectively. The first center is related to carbon vacancies and the second to silicon interstitials.

In this paper, fired and non-fired direct PECVD deposited Si-SiNx interface properties with and without NH3 pretreatment on both n- and p-type mono-crystalline silicon samples were investigated with deep-level transient spectroscopy (DLTS) measurements. A and B defect states are identified at the Si-SiNx interface. Energy-dependent electron and hole capture cross sections were measured by small-pulse DLTS. Fired samples with NH3 pretreatment show the lowest DLTS signals, which suggests the lowest overall Dit. The combination of NH3 pretreatment and firing is also suggested for application in the solar cell fabrication.

Planar Pt/AlGaN/GaN Schottky barrier diodes (SBDs) have been characterized by capacitance-voltage and capacitance deep-level optical spectroscopy measurements, compared to reference Pt/GaN:Si SBDs. Two specific deep levels are found to be located at ∼1.70 and ∼2.08 eV below the conduction band, which are clearly different from deep-level defects (Ec - 1.40, Ec - 2.64, and Ec - 2.90 eV) observed in the Pt/GaN:Si SBDs. From the diode bias dependence of the steady-state photocapacitance, these levels are believed to stem from a two-dimensional electron gas (2DEG) region at the AlGaN/GaN hetero-interface. In particular, the 1.70 eV level is likely to act as an efficient generation-recombination center of 2DEG carriers.

High electron mobility transistors (HEMTs) based on AlGaN-GaN hetero-structures are promising for high power, high speed, and high temperature operation. Especially, AlGaN-GaN HEMTs grown on semi-insulating (SI) SiC substrates are the most promising for both military and commercial applications. High performance characteristics from these devices are possible in part due to the presence of high two-dimensional electron gas charge sheet density maintaining a high Hall mobility at the AlGaN barrier-GaN buffer hetero-interface and in part due to high thermal conductivity of the SiC substrates. However, long-term reliability of these devices still remains a major concern because of the large number of traps and defects present both in the bulk as well as at the surface leading to undesirable characteristics including current collapse. We report on the study of traps and defects in two MOCVD-grown structures: Al0.27Ga0.73N HEMTs on SI SiC substrates and Al0.27Ga0.73N Schottky diodes on conducting SiC substrates. Our HEMT structures consisting of undoped AlGaN barrier and GaN buffer layers grown on an AlN nucleation layer show a charge sheet density of ∼1013/cm2 and a Hall mobility of ∼1500cm2/V·sec. Deep level transient spectroscopy (DLTS) was employed to study traps in AlGaN Schottky diodes and HEMTs fabricated with different Schottky contacts consisting of Pt/Au and Ni/Au. Focused ion beam was employed to prepare both cross-sectional and plan view TEM samples for defect analysis using a high resolution TEM.

An effect of the nitrogen concentration on the concentrations of deep-level defects in bulk 6H-SiC single crystals is investigated. Six electron traps labeled as T1A, T1B, T2, T3, T4 and T5 with activation energies of 0.34, 0.40, 0.64, 0.67, 0.69, and 1.53 eV, respectively, were revealed. The traps T1A (0.34 eV) and T1B (0.40 eV), observed in the samples with the nitrogen concentration ranging from ∼2×1017 to 5×1017 cm−3, are attributed to complexes formed by carbon vacancies located at various lattice sites and carbon antisites. The concentrations of traps T2 (0.64 eV) and T3 (0.67 eV) have been found to rise from ∼5×1015 to ∼1×1017 cm−3 with increasing the nitrogen concentration from ∼2×1017 to ∼2.0×1018 cm−3. These traps are assigned to complexes involving silicon vacancies occupying hexagonal and quasi-cubic sites, respectively, and nitrogen atoms. The trap T4 (0.69 eV) concentration also substantially rises with increasing the nitrogen concentration and it is likely to be related to complexes formed by carbon antisites and nitrogen atoms. The midgap trap T5 (1.53 eV) is presumably associated with vanadium contamination. The presented results show that doping with nitrogen involves a significant change in the defect structure of 6H-SiC single crystals.

Ion implantation doping of Si through an SiO2 overlayer is of interest for fabrication of a range of devices on the pathway to development of a solid–state quantum computer (SSQC). The fabrication requirements of devices based on the Kane architecture typically involve implantation through a pre-existing thin device–quality thermal oxide at low fluences ∼1011 cm−2 and ion energies in the range 10 – 20 keV. Here we present results from a deep level transient spectroscopy studies of ion–implanted MOS capacitors in which interface–trap densities have been measured in as–grown and H–passivated thermal oxides and in ion implanted and rapid–thermally processed devices. For thin oxides of 5nm or less and low ion fluences we find that implantation does not significantly increase interface trap densities and somewhat surprisingly that it can even be beneficial when the interface trap density is abnormally high, (∼ 1 × 1011cm−2.eV−1) in the as-grown oxide.

Deep level electron traps in n-GaN grown by metal organic vapor phase epitaxy (MOVPE) on Si (111) substrate were studied by means of deep level transient spectroscopy (DLTS). The growth of n-GaN on different pair number of AlN/GaN superlattice buffer layers (SLS) system and on c-face sapphire substrate are compared. Three deep electron traps labeled E4 (0.7-0.8 eV), E5 (1.0-1.1 eV), were observed in n-GaN on Si substrate. And the concentrations of these traps observed for n-GaN on Si are very different from that on sapphire substrate. E4 is the dominant of these levels for n-GaN on Si substrate, and it behaves like point-defect due to based on the analysis by electron capture kinetics, in spite of having high dislocation density of the order of 1010 cm−3.

Interface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.

In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.

Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).

Unintentionally doped n-type ZnO single crystals were implanted by nitrogen ions with different fluences of 1013, 1014 and 1015 cm−2 respectively. ZnO p-n homojunction was successfully fabricated due to the formation of p-type layer after 650°C post-implantation annealing in air for 30 minutes. Further thermal evolution of deep level defects was studied through thermal annealing up to 1200°C. Electrical characterization techniques including current-voltage (I-V), capacitance-voltage (C-V), Deep Level Transient Spectroscopy (DLTS) and double-correlation DLTS (DDLTS) were used for investigating the control sample, all the as-implanted and annealed samples through Au/n-ZnO Schottky diodes as well as ZnO p-n junctions. Detailed electrical properties of fabricated devices and characteristics of implantation induced defects were analyzed based on plentiful DLTS spectra. Moreover, low-temperature photoluminescence experiments of all the as-implanted and annealed samples were performed and the correlation between results from electrical and optical characterizations was discussed.

We discuss the possibilities of analysis of electrically active defects in semiconductors and dielectrics by means of Isothermal Capacitance-Transient Spectroscopy and Isothermal Charge-Transient Spectroscopy, applied on sub-micrometer scale. While the first of them utilizes the relaxation of the depletion layer, caused by emission of trapped charges and requires sufficient conductivity, the second directly integrates the transient current and can be applied also to low-conductivity materials like dielectrics.

We present some results obtained on pentacene thin films. By means of our charge-transient spectrometer we have achieved a resolution of hundreds of electrons but we believe it can be further improved approximately by one order of magnitude. In materials with relatively high defect concentration, using optimal shape of the probe, a resolution on the order of tens of manometers can be achieved. At low defect concentrations, e.g. in device quality silicon, a resolution on the hundred-nm level is expected.

Deep level transient spectroscopy (DLTS) is the best technique for monitoring and characterizing deep levels introduced intentionally or occurring naturally in semiconductor materials and complete devices. DLTS has the advantage over all the techniques used to-date in that it fulfils almost all the requirements for a complete characterization of a deep centre and their correlation with the device properties.In particular the method can determine the activation energy of a deep level, its capture cross-section and concentration and can distinguish between traps and recombination centers.

In this invited paper we provide an overview of the extensive R & D work that has been carrier out by the authors on the identification of the recombination and compensator centers in Si and III-V compound materials for space solar cells. In addition, we present an overview of key problems that remain in the understanding of the role of the point defects and their correlation with the solar cell parameters.

Two cast multi-crystalline silicon (mc-Si) sister wafers before and after solar cell processing were investigated to explore the gettering effect in low and high density structural defect regions.For the processed wafer, the minority carrier recombination lifetime was correlated to the structural defect distribution.For the low density region of as-grown wafer, Cr impurities were 3.28x1013cm-3 and they were reduced to 1.74×1012cm−3 for the processed wafer.The isolated Cr impurities dissolved from the precipitates at 900°C which is the typical gettering temperature in the solar cell processing are getterd effectively in the low density regions.Our current understanding for the gettering effect in the high density regions is that the segregated Cr impurities at defect sites are not released to the silicon matrix at 900°C resulting in the poor gettering effect.