Copper CMP is emerging as the next generation process technology enabling feature size reduction to .15μm and beyond[1]. We propose a copper removal mechanism in the context of a slurry consisting of an oxidizer and an abrasive. The body of evidence suggests that we are polishing in an oxidation complex rate limited regime. We observed low removal rate of copper in the absence of either oxidizer or abrasive, but rate was still dependent on CMP parameters and strongly tied to temperature. Any proposed mechanism must explain the observed dependence of rate on CMP aggressiveness and the role of each of the components. For the slurry used in this work we propose that an increase in temperature resulting from an increase in CMP intensity drives the kinetics of the oxidation reaction, and that the removal process can be classified as temperature-activated, abrasion assisted dissolution.

An investigation was undertaken to characterize the electrochemical behavior of copper in tetramethyl ammonium hydroxide (TMAH) based solutions. The effect of hydrogen peroxide and abrasion with a polyvinyl alcohol (PVA) brush on the corrosion of copper in alkaline solutions were characterized. Galvanic interactions between copper and tantalum in TMAH as well as in ammonium hydroxide (NH4OH) solutions were investigated. The experimental results have shown that the corrosion of copper in TMAH is lower than that in NH4OH, especially at pH values higher than 10. Even in the presence of hydrogen peroxide, TMAH corrodes copper at a lower rate than NH4OH.

Various options that afford control of the TEOS, W, and Cu/barrier polishes were explored in the building of multilevel dual inlaid structures. Improved tool performance that enables more sophisticated down pressure control with higher resolution backpressure adjustments was employed for the oxide module to control the interlevel capacitances. Planarity at both the global and local levels at the oxide polish affords a good starting point for successive builds without metal pooling. In W CMP, small and controllable oxide erosion and plug recess was obtained with harder polishing pads. In Cu/barrier CMP, the tight overpolish/underpolish margin was maintained by head control and appropriate endpoint algorithms. A six-level build with tight and low sheet resistances and leakages was demonstrated.

The purpose of this study was to explore the interaction between slurry particles and wafer surfaces by the measurements of their zeta potentials. The zeta potentials of slurry particles such as fumed and colloidal silica, alumina, ceria and MnO2 and substrates such as silicon, TEOS, W, and Al have been measured by electrophoretic and electroosmosis method to evaluate the electrical properties of surfaces, respectively. The zeta potential of oxide and metal surfaces showed similar values to those of particles as a function of pH. The interaction energy between alumina and silica particles and TEOS, W and Al substrate were calculated based on DLVO theory. No deposition of silica particles on TEOS and the heavy deposition of alumina particles on metal substrates were observed in the particle deposition test. Experimental results were well agreed with the theoretical calculation.

The flow of a slurry in a CMP process has been investigated. This wafer-scale model provides the three dimensional flow field of the slurry, the spatial distribution of the local shear rate imposed on the wafer surface, and the streamline patterns which reflect the transport characteristics of the slurry.

We have found that the entrainment of a slurry between a silicon surface and a polyurethane pad will cause the generation of subambient pressure at that interface. These pressures cause the silicon to be further impressed into the pad. We have measured these pressures and this paper reports on the pressure distribution maps over an area beneath a 100mm diameter silicon wafer. The pressures are generally not uniform. The leading 2/3 of the wafer has subambient pressures of the order of 50kPa and the trailing 1/3 of the wafer has positive pressures of approximately 10kPa. The reasons for the subambient pressures is related to the dynamics of the compression of pad asperities, the boundary effects of the silicon edge, the rebound of the asperities, and re-infiltration of the slurry.

In previous work, we have formalized the notions of “planarization length” and “planarization response function” as key parameters that characterize a given CMP consumable set and process. Once extracted through experiments using carefully designed characterization mask sets, these parameters can be used to predict polish performance in CMP for arbitrary product layouts. The methodology has proven effective at predicting oxide interlevel dielectric planarization results.

In this work, we discuss extensions of layout pattern dependent CMP modeling. These improvements include integrated up and down area polish modeling; this is needed to account for both density dependent effects, and step height limits or step height perturbations on the density model. Second, we discuss applications of the model to process optimization, process control (e.g. feedback compensation of equipment drifts), and shallow trench isolation (STI) polish. Third, we propose a framework for the modeling of pattern dependent effects in copper CMP. The framework includes “removal rate diagrams” which concisely capture dishing height and step height dependencies in dual material polish processes.

A planarization monitor has been applied to the copper system to investigate pattern dependencies during copper overburden planarization. Conventional profilometry and a noncontact, acousto-optic measurement tool, the Insite 300, are utilized to quantify the planarization performance in terms of the defined step-height-reduction-ratio (SHRR). Illustrative results as a function of slurry, pad type and process conditions are presented. For a typical stiff-pad copper CMP process, we determined the planarization distance to be approximately 2mm.

The change of surface profile during chemical-mechanical planarization (CMP) is monitored continuously in this study. The influences from pattemn dependency and substrate effects are discussed. Step height reduction rate is a function of pattern density and down force. The rate decreases with time until planarization is achieved. As the polish approaches the patterns underneath, the interaction between substrate effects and pattern dependency results in the resurgence of step height. The implication of this newly found phenomenon is discussed.

Shallow-Trench Isolation (STI) relies on integrated process optimization to achieve the requirement of chip-level process variation across different device features. Characterization of pattern density dependency was investigated through Chemical Mechanical Polishing (CMP) process optimization by Design of Experiment (DOE) and modification of masks by adding dummy structure. Four mask sets with different device features and pattern densities were tested. Effects of slurry selectivity, over-polish extent, silicon trench depth, high-density plasma film thickness, and dummy structure were evaluated. Correlation between physical and electrical data illustrates the process margin in which both logic and memory devices could perform their respective functions. KEYWORDS: Shallow-Trench Isolation, System-on-a-Chip, Pattern Density, Chemical-Mechanical Polishing.

In the CMP planarization process, detecting the final polishing point is extremely important for maintaining high yield rates. Therefore, various methods for detecting the final polishing point have been developed.

We consider it vital that the SiO2 film thickness across a representative area be measured extremely precisely at high speed in the final stages to accurately control film polishing. However, up until now there has not been any wholly satisfactory method to achieve this.

In order to measure a fine representative film area (test pattern) both rapidly and accurately, we concluded that the non-contact, non-destructive and highly reliable methods of spectrometric analysis were most promising.

Based on these considerations, we developed a compact spectrometric film thickness measurement system which can accurately inspect test patterns at high speeds and installed it adjacent to the CMP equipment's polishing table. Using this system as a film thickness monitor, we can now measure film thickness while rinsing away slurry contaminants, halt polishing at any stage, and calculate the remaining polishing time from the current and desired thicknesses.

This system's pattern identification function can automatically measure the film thickness with very fine test patterns (as small as 40 square microns). When used with SiO2 single layer films, the experimental prototype's measurements proved reliably reproducible (showing a deviation of less than 4 nm at 3 σ over repeated trials), and required thirty seconds or less per wafer (including time for pre-alignment and five-point measurement). The system's theoretical basis and actual operations are described below.

Non contact cleaning or wet-cleaning processes, were the megasonic play a key role in the separation of the particles from the wafer is a commonly used technique in semiconductor manufacturing. CMP process can be very damaging to the production yield if not followed by an effective post clean process. McQueen identified the effect of the acoustic boundary layer and its role in the removal of small particles at high frequency. Busnaina et alt studied ultrasonic and megasonic particle removal and the effect of acoustic streaming. They showed that the cleaning efficiency increased with power until a certain range and then decrease slightly. Busnaina et al result indicted that SCI removes more particles than DI water particularly at lower megasonic powers specially in the case were the slurry particles are deposited onto the wafer surface by dipping experiments. But they also demonstrated that it was possible to achieve 100 % removal in DI water when using the optimum conditions. This paper presents the latest results of the post-CMP megasonic cleaning process, this study is focused on the cleaning of thermal oxide silicone wafer polished using silica based slurry and cleaned using diluted SC1 (H20/H202/NH4OH: 40/2/1).

CMP has been revealed as an attractive technique to poly Si of trench planalizing process. Major issues of process integration for that purpose have been post-CMP cleaning process. A new post CMP cleaning process which employed special organic surfactant has been reported in this paper. In general, wafers after CMP process are contaminated by particles and metallic impurities in the case of conventional cleaning method. The contamination introduce the defects into the wafers after oxidation. The contamination was removed by new cleaning method. using DI water containing special organic surfactant and silica particles. The experimental work has focused on critical problems that had to be solved, using AFM, EDX and VPDICP/MS.

Residual subsurface damages introduced by mirror polishing into Si CZ wafers degrade GOI in ULSI MOS devices. A removal of the damage throughout 9 times SC1 cleaning was systematically characterized as correlated between PCA signals measured by noncontact UV/mmwave technique, GOI at 10MV/cm for MOS diodes with a thin gate-oxide thickness of 10nm, surface microroughness Ra measured by AFM. The same characterization was carried out for epitaxial wafers, as reference. Degraded GOI and PCA signal were recovered throughout 3 times SC1 cleaning and did not depend on Ra of 0.1–0.2 nm, which led to that the damage causes the degradation of GOI, but it can be removed by 3 times SC1 cleaning, and the damage depth was about 21nm. Further, the PCA signal well reflects to removal of the damage and degradation of GOI so that it can be a monitor for characterizing the removal and GOI. Direct observation of the damage using OSDA was carried out for the epitaxial wafer polished and SC1 cleaned. The OSDA indicated an image involving straight lines which disappeared after 3 times SC1 cleaning. This gave a direct evidence for catching up it by PCA and existence of residual subsurface damages.

Wet cleaning of wafers during the semiconductor production process often requires uniform removal of a few nanometers of material. Ideally, a single cleaning chemistry can be found that etches all exposed features at a comparable rate. Etch rates near 1 nm/min are desired for batch process and near 10 nm/min for single-wafer processes. A mixture of 500:1 DHF (dilute HF) with dissolved oxygen controlled near parts-per-million (ppm) levels has been found to meet these requirements for post copper CMP (chemical-mechanical polishing) cleans with exposed SiO2 and Cu metal.

We employ salt particles deposited on soda lime glass substrates as a model system for particle detachment in chemically active environments. The chemical activity is provided by water vapor, and detachment is performed with the tip of a scanning force microscope. The later force required to detach nanometer-scale salt particles is a strong function of particle size and relative humidity. The peak lateral force at detachment divided by the nominal particle area yields an effective interfacial shear strength. The variation of shear strength with particle size and humidity is described in terms of chemically assisted crack growth along the salt-glass interface.